Semiconductor device with schottky electrode having high schottky barrier

• US 20020017696A1
• Filed: 06/28/2001
• Published: 02/14/2002
• Est. Priority Date: 06/29/2000
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Ohno, Yasuo, Takahashi, Yuji, Miyamoto, Hironobu, Kasahara, Kensuke, Nakayama, Tatsuo, Ando, Yuji, Hayama, Nobuyuki, Kunihiro, Kazuaki, Kuzuhara, Masaaki, Matsunaga, Kouji
• Granted Patent: US 6,492,669 B2
• Time in Patent Office: Days
• US Class Current: 257/471
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/475 on AIII-BV compounds
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material

Abstract

A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.

Claims

1. A semiconductor device comprising:

a first electron barrier layer;

a second electron barrier layer that is formed on said first electron barrier layer either directly or on an interposed spacer layer and in which a negative piezoelectric charge is induced on said first electron barrier layer side and a positive piezoelectric charge is induced on the opposite side; and

a Schottky electrode that is formed on the side of said second electron barrier layer in which said positive piezoelectric charge is induced.

2. A semiconductor device according to claim 1, wherein a negative piezoelectric charge is induced in said second electron barrier layer side of said first electron barrier layer and a positive piezoelectric charge is induced on the opposite side of said first electron barrier layer.

3. A semiconductor device according to claim 1, wherein said first electron barrier layer and said second electron barrier layer are both composed of III-nitride semiconductor materials.

4. A semiconductor device according to claim 2, wherein said first electron barrier layer and said second electron barrier layer are both composed of III-nitride semiconductor materials.

11. A semiconductor device according to claim 1, wherein said Schottky electrode is a gate electrode, and further comprising a source electrode and a drain electrode.

12. A semiconductor device according to claim 11, wherein said source electrode and said drain electrode are formed in contact with a III-nitride semiconductor layer that has no strain or that has tensile strain.

14. A semiconductor device according to claim 13, wherein said source electrode and said drain electrode are formed in contact with a III-nitride semiconductor layer that has no strain or that has tensile strain.

16. A semiconductor device according to claim 15, wherein said source electrode and said drain electrode are formed in contact with a III-nitride semiconductor layer that has no strain or that has tensile strain.

5. A semiconductor device comprising:

a base layer that is a wurtzite III-nitride semiconductor layer in which the (0001) plane is the principal plane;

a first electron barrier layer that is formed on said base layer and that is a wurtzite III-nitride semiconductor layer in which the (0001) plane is the principal plane;

a second electron barrier layer formed on said first electron barrier layer either directly or on an interposed spacer layer, said second electron barrier layer being a wurtzite III-nitride semiconductor layer in which the (0001) plane is the principal plane and having compressive strain; and

a Schottky electrode that is formed on said second electron barrier layer.

6. A semiconductor device according to claim 5, wherein said first electron barrier layer has tensile strain.

13. A semiconductor device according to claim 5, wherein said Schottky electrode is a gate electrode and further comprising a source electrode and a drain electrode.

7. A semiconductor device comprising:

a base layer that is a wurtzite III-nitride semiconductor layer in which the (0001) plane is the principal plane;

a first electron barrier layer that is formed on said base layer that is a wurtzite III-nitride semiconductor layer in which the (0001) plane is the principal plane;

a second electron barrier layer that is formed on said first electron barrier layer either directly or on an interposed spacer layer, said second electron barrier layer being a wurtzite III-nitride semiconductor layer in which the (0001) plane is the principal plane, and having a greater average lattice constant than that of said base layer, where the average lattice constant is defined as the average value of the lattice constant in the horizontal plane that is perpendicular to the direction of film thickness; and

a Schottky electrode that is formed on said second electron barrier layer.

8. A semiconductor device according to claim 7, wherein the average lattice constant of said first electron barrier layer is equal to or smaller than the average lattice constant of said base layer.

9. A semiconductor device according to claim 8, wherein:

said base layer is composed of Al_α

Ga<sub>(1−

α

)</sub>N;

(0≦

α

≦

1);

said first electron barrier layer is composed of Al_β

Ga<sub>(1−

β

)</sub>N;

(α

≦

β

≦

1); and

said second electron barrier layer is composed of In_xGa_yAl<sub>(1−

x−

y)</sub>N;

(0<

x≦

1, 0≦

y≦

1).

10. A semiconductor device according to claim 8, wherein:

said base layer is composed of Al_α

Ga<sub>(1−

α

)</sub>N;

(0<

α

≦

1);

said first electron barrier layer is composed of Al_β

Ga<sub>(1−

β

)</sub>N;

(α

≦

β

≦

1); and

said second electron barrier layer is composed of Al_γ

Ga<sub>(1−

γ

)</sub>N;

(0≦

γ

≦

α

).

15. A semiconductor device according to claim 7, wherein said Schottky electrode is a gate electrode and further comprising a source electrode and a drain electrode.

17. A semiconductor device comprising:

a plurality of wurtzite III-nitride semiconductor layers in which the (0001) plane is the principal plane including a first layer composed of GaN and a second layer composed of Al_xGa<sub>(1−

x)</sub>N;

(0<

x≦

1);

a gate electrode that is formed on said III-nitride semiconductor layers so as to contact said first layer; and

a source electrode and a drain electrode formed on said III-nitride semiconductor layers so as to contact said second layer.