METHOD AND APPARATUS FOR GLITCH PROTECTION FOR INPUT BUFFERS IN A SOURCE-SYNCHRONOUS ENVIRONMENT

• US 20020017944A1
• Filed: 12/01/1999
• Published: 02/14/2002
• Est. Priority Date: 03/19/1998
• Status: Active Grant

• Current Assignee: Alper Ilkbahar
• Original Assignee: Alper Ilkbahar
• Inventors: ILKBAHAR, ALPER
• Granted Patent: US 6,433,600 B2
• Time in Patent Office: Days
• US Class Current: 327/379
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H03K 5/153 Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant switching at zero crossing H03K17/13
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

A method and apparatus for glitch protection for differential strobe input buffers in a source-synchronous environment. The present invention provides a solution to the problem of noise sensitivity of differential strobe input buffers in a source-synchronous environment, which may cause functional problems. The present invention enables the use of fully differential strobe signals to improve electrical performance of the source synchronous data transfers while removing the noise sensitivity problem associated with these signals. This is accomplished by providing a glitch protection circuit that provides protection against input glitches for a first predetermined period of time after each strobe transition. The present invention also provides a detection circuit that detects when both differential strobe signals are in the same logic state, which corresponds to a transition between bus masters (a dead cycle). The detection circuit causes the glitch protection circuit to latch the output signal of the glitch detection circuit.

Claims

1. A method comprising the steps of:

receiving a pair of strobe signals;

latching the strobe signals for a first predetermined period of time in response to state transitions;

determining whether both of the strobe signals are of equivalent logic state;

generating a latching signal in response to both strobe signals being of equivalent logic state; and

latching the strobe signals in response to the latching signal.

2. The method of claim 1, further comprising the step of delaying the latching signal for a second predetermined length of time prior to the step of latching the strobe signal in response to the latching signal.

3. The method of claim 2, wherein the first length of time is greater than the second length of time.

4. The method of claim 1, further comprising:

detecting whether the strobe signals are of an opposite logic state; and

disabling the latching signal in response to detecting that the strobe signals are of an opposite logic state, if the latching signal is enabled.

5. A circuit comprising:

means for receiving a pair of strobe signals;

means for providing glitch protection to the strobe signals by latching the strobe signals for a first predetermined period of time in response to state transitions;

means for determining whether both of the strobe signals are of equivalent logic state;

means for generating a latching signal in response to both strobe signals being of equivalent logic state; and

means for latching the strobe signals in response to the latching signal.

6. The circuit of claim 5, further comprising means for delaying the latching signal for a second predetermined length of time prior latching the strobe signal in response to the latching signal.

7. The circuit of claim 6, wherein the first length of time is greater than the second length of time.

8. The circuit of claim 5, further comprising:

means for detecting whether the strobe signals are of an opposite logic state; and

means for disabling the latching signal in response to detecting that the strobe signals are of an opposite logic state, if the latching signal is enabled.

9. A circuit comprising:

a set of input buffers coupled to receive a pair of differential strobe signals;

first and second detection circuits coupled to receive a set of output signals from the set of input buffers, the first and second detection circuits generating a latch signal in response to the output signal from the set of input buffers indicating that the pair of differential strobe signals are in equivalent logic states; and

first and second glitch protection circuits coupled to the first and second detection circuits, the first and second glitch protection circuits generating output strobe and complemented output strobe signals, respectively, the first and second glitch protection circuits latching the respective output strobe signals for a first predetermined length of time after a strobe transition.

10. The circuit of claim 9, wherein the set of input buffers comprises:

a first differential input buffer coupled to receive a strobe signal and a complemented strobe signal;

a first pseudo-differential input buffer coupled to receive the strobe signal and a reference voltage;

a second differential input buffer coupled to receive the complemented strobe signal and the strobe signal; and

a second pseudo-differential input buffer coupled to receive the complemented strobe signal and the reference voltage.

11. The circuit of claim 10, wherein the first and second detection circuits comprise:

a first AND gate coupled to receive as inputs outputs of the first and the second pseudo-differential input buffers; and

a second AND gate coupled to receive as inputs the outputs of the first and the second pseudo-differential input buffers.

12. The circuit of claim 10, wherein the first and second detection circuits comprise:

a first NAND gate coupled to receive as inputs outputs of the first and the second pseudo-differential input buffers; and

a second NAND gate coupled to receive as inputs the outputs of the first and the second pseudo-differential input buffers.

13. The circuit of claim 9, wherein the first and second detection circuits provide the latch signal a second predetermined time after the strobe and the complemented strobe signals reach the equivalent logic state.

14. The circuit of claim 13, wherein the first predetermined period of time is greater than the second predetermined period of time.

15. The circuit of claim 13, wherein the latch signal is disabled in response to the strobe signal and the complemented strobe signal being in different logic states.

17. The computer system of claim 16, wherein the first predetermined period of time is greater than the second predetermined period of time.

18. The computer system of claim 16, wherein the latching signal is disabled in response to the pair of strobe signals being in different logic states, if the latching signal is enabled.

19. The computer system of claim 16, wherein the component is a dynamic memory device.

20. The computer system of claim 16, wherein the component is an I/O device.

16. A computer system comprising:

an externally terminated bus;

a processor coupled to the bus having a source synchronous bus interface; and

a component coupled to the bus having a source synchronous bus interface comprising glitch protection circuitry having

a plurality of differential input buffers, each receiving a pair of strobe signals,

a glitch protection circuit coupled to each output of each differential input buffer, the glitch protection circuit latching the output signal received for a first predetermined period of time in response to the output signal received changing logic states,

a plurality of pseudo-differential input buffers, each receiving a reference signal and one of the pair of strobe signals, and

a detection circuit coupled to each output of each pseudo-differential input buffer, the detection circuit generating a latching signal in response to the pair of strobe signals input to the source synchronous bus interface having equivalent logic states, wherein the latching signal is generated a second predetermined period of time after the strobe signals reach equivalent logic states.