Method for reading nonvolatile semiconductor memory configurations

• US 20020018366A1
• Filed: 03/13/2001
• Published: 02/14/2002
• Est. Priority Date: 03/13/2000
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Schuler, Franz, von Schwerin, Andreas Graf, Kowarik, Oskar
• Granted Patent: US 6,407,945 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A method for reading non-volatile semiconductor memory configurations includes determining a high threshold voltage and a low threshold voltage based on a charge state of a floating gate for a transistor, and applying a reverse bias between a bulk and a source of the transistor during reading.

Claims

1. A method for reading non-volatile semiconductor memory configurations, which comprises:

determining a high threshold and a low threshold voltage based on a charge state of a floating gate for a transistor; and

applying a reverse bias between a bulk and a source of the transistor during reading.

2. The method according to claim 1, which further comprises

permitting the low threshold voltage to assume negative voltage values for NMOS transistors;

and

permitting the low threshold voltage to assume positive voltage values for PMOS transistors.

3. The method according to claim 1, which further comprises expanding the window between the high threshold voltage and the low threshold voltage by applying the reverse bias.

4. The method according to claim 1, which further comprises maintaining constant the window between the high threshold voltage and the low threshold voltage by applying the reverse bias.

5. The method according to claim 1, which further comprises shifting a threshold voltage for NMOS transistors by γ

({square root}{square root over (−

V_SB+2φ

_f)}−

{square root}{square root over (2φ

_f)}) and shifting a threshold voltage for PMOS transistors by −

γ

({square root}{square root over (V_SB−

2φ

_f)}−

{square root}{square root over (−

2φ

_f)}) by applying the bias, where γ

is the substrate control factor and φ

_f is the Fermi voltage of the bulk.

6. The method according to claim 1, which further comprises placing each of a drain of the transistor and the source of the transistor at different potentials when the reverse bias has been applied.