Memory

• US 20020018513A1
• Filed: 04/06/2001
• Published: 02/14/2002
• Est. Priority Date: 05/15/1990
• Status: Abandoned Application

• Current Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Zanders, Gary V., Lehmann, Guenter H., Curry, Stephen M., Deierling, Kevin E., Payne, William Lee II, Lee, Robert D., Kurkowski, Hal, Bolan, Michael L., Dias, Donald R.
• Application Number:
  US09/827,825
• Publication Number:
  US 20020018513A1
• Time in Patent Office: Days
• US Class Current: 374/178
• CPC Class Codes: G01K 1/028 arrangements for numerical indication
• CPC Class Codes: G01K 3/10 in respect of time, e.g. reacting only to a quick change of temperature
• CPC Class Codes: G01K 7/245 in an oscillator circuit
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 3/0383 Signal control means within the pointing device
• CPC Class Codes: G06F 3/04897 Special input arrangements or commands for improving display capability
• CPC Class Codes: G06K 19/07 with integrated circuit chips
• CPC Class Codes: G06K 7/0021 for reading/sensing record carriers having surface contacts
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Serial bus modules with unique multibit identifications that may be searched with multiple modules on a single bus. Modules may contain temperature history per integrated Arrhenius temperature dependent signal. Modules may be packaged as tokens or as two or three lead plastic plastic, also with the three lead packages further functionality as sensors or switches may be incorporated into the modules.

Claims

1. A serial-port memory;

comprising;

(a) a serial port;

(b) a scratchpad memory coupled to said serial port;

(c) a second memory coupled to said scratchpad memory; and

(d) control logic coupled to said serial port and said scratchpad and second memories, said control logic transfers information from said scratchpad memory to said second memory as a block pursuant to a block transfer command received at said serial port.

2. The memory of claim 1, wherein:

(a) said serial port, scratchpad memory, second memory, and control logic are in a package with only two electrical contacts.

3. The memory of claim 2, wherein:

(a) said package is a token-shaped container with the two planar surfaces providing said two electrical contacts.

4. The memory of claim 1, wherein:

(a) said control logic only transfers information to said second memory after a password identifying said second memory has been received at said serial port.

5. The memory of claim 1, wherein:

(a) said control logic includes a cyclic redundancy check generator.

6. The memory of claim 1, further comprising:

(a) third and fourth memories coupled to said scratchpad memory; and

(b) wherein said control logic transfers information as a block from said scratchpad memory to one of said second, third, and fourth memories pursuant to a block transfer command received at said serial port.

7. A system with identifiable modules on a serial bus, comprising:

(a) a bus master;

(b) a serial bus coupled to said bus master;

(c) a plurality of modules, each of said modules coupled to said bus, and each of said modules having a unique n-bit identification.

(d) each of said modules having control logic programmable to respond to a command sequence of first read, second read, write on said bus from said bus master by (i) responding to said first read by signalling to said bus a jth bit of said identification, (ii) responding to said second read by signalling to said bus the complement of said jth bit, and (iii) responding to said write by comparing said write'"'"'s bit to said jth bit and (A) when said write'"'"'s bit differs from said jth bit, then idling said module or (B) when said write'"'"'s bit matches said jth bit, then incrementing to the j+1)st bit of said identification if j is less than n.

8. The system of claim 7, wherein:

(a) said n-bit identification has 64 bits; and

(b) when 64 iterations of the command sequence first read, second read, and write of step (d) of claim 7 yield 64 consecutive write'"'"'s bit matching the corresponding identification bit of a first module, said bus master can program a command into said control logic of said first module.

9. The system of claim 7, wherein:

(a) each of said modules having control logic programmable to respond to a command write on said bus from said bus master by comparing said write'"'"'s bit to said jth bit and (A) when said write'"'"'s bit differs from said jth bit, then idling said module or (B) when said write'"'"'s bit matches said jth bit, then incrementing to the (j+1)st bit of said identification if j is less than n.

10. The system of claim 9, wherein:

(a) said n-bit identification has 64 bits; and

(b) when 64 iterations of the command write of step (a) of claim 9 yield 64 consecutive write'"'"'s bit matching the corresponding identification bit of a first module, said bus master can program a command into said control logic of said first module.

11. The system of claim 7, wherein:

(a) each of said modules having control logic programmable to respond to a command read on said bus from said bus master by signalling the jth bit of said n-bit identification and then incrementing to the (j+1)st bit of said identification if j is less than n.

12. The system of claim 11, wherein:

(a) said n-bit identification has 64 bits; and

(b) when 64 iterations of the command read of step (a) of claim 11 said bus master can program a command into said control logic of said first module.

14. The temperature sensor of claim 13, wherein:

(a) said signal includes the current through a p-n junction; and

(b) said integrator includes a current-to-frequency converter which drives a counter.

15. The sensor of claim 13, wherein:

(a) said constant Tc is programmable.

13. A temperature sensor, comprising:

(a) a device which provides a signal depending upon absolute temperature T substantially proportional to exp(−

Tc/T) where Tc is a constant;

(b) an integrator which samples said signal and accumulates said samples;

(c) an output coupled to said integrator.