SUPER SELF-ALIGNED TRENCH-GATE DMOS WITH REDUCED ON-RESISTANCE

• US 20020019099A1
• Filed: 04/22/1999
• Published: 02/14/2002
• Est. Priority Date: 04/22/1999
• Status: Active Grant

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: WILLIAMS, RICHARD K., GRABOWSKI, WAYNE
• Granted Patent: US 6,413,822 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A novel super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Claims

1. A process for fabricating a trench MOSFET comprising:

providing a body of semiconductor material having a surface;

forming a first mask over the surface, the first mask having an opening where a trench is to be located in the body;

etching the semiconductor material through the opening in the first mask to form a trench in the semiconductor body;

forming a first oxide layer in the trench;

introducing polysilicon into the trench;

with the first mask in place, oxidizing an exposed surface of the polysilicon to form a second oxide layer at the top of the trench, the second oxide layer extending down into the trench;

removing the first mask; and

depositing a metal layer on a surface of the second oxide layer and the surface of the body.

2. The method of claim 1 wherein forming a first mask comprises depositing a nitride layer.

3. The method of claim 2 comprising forming a third oxide layer between the surface of the body and the nitride layer.

4. The method of claim 2 wherein at least a portion of the third oxide layer remains after the first mask is removed.

5. The method of claim 4 comprising removing the third oxide layer.

6. The method of claim 3 wherein the second oxide layer is thicker than each of the first and third oxide layers.

7. The method of claim 1 wherein the second oxide layer is thicker than the first oxide layer.

8. The method of claim 1 comprising depositing oxide in the trench and etching the oxide back to form a fourth oxide layer on a bottom of the trench.

9. The method of claim 8 wherein depositing oxide comprises depositing oxide by a chemical vapor deposition process.

10. The method of claim 9 wherein each of the second and fourth oxide layers is thicker than each of the first or third oxide layers.

11. The method of claim 1 comprising etching the polysilicon until a surface of the polysilicon is coplanar with the surface of the body.

12. The method of claim 1 wherein providing a body of semiconductor material comprises growing an epitaxial layer on a surface of a semiconductor substrate.

13. The method of claim 12 comprising implanting dopant of a first conductivity type through solid portions of the first mask to form a body region in the epitaxial layer.

14. The method of claim 13 comprising implanting dopant of a second conductivity type through solid portions of the first mask to form a source region in the epitaxial layer.

15. The method of claim 1 wherein introducing polysilicon into the trench comprises:

introducing a first polysilicon layer into the trench;

etching the first polysilicon layer until an exposed surface of the first polysilicon layer is at a level below the surface of the semiconductor body;

introducing a second polysilicon layer over the first polysilicon layer, the second polysilicon layer covering the first polysilicon layer and the first mask.

16. The method of claim 1 comprising forming a second mask over the polysilicon layer, the second mask having an opening over the trench, and comprising etching the polysilicon layer through the opening in the second mask, thereby leaving a remaining portion of the polysilicon layer extending laterally over the surface of the semiconductor body.

17. The method of claim 16 comprising:

implanting dopant of a first conductivity type into the remaining portion of the polysilicon layer;

forming a third mask with an opening over the remaining portion of the polysilicon layer;

implanting dopant of a second conductivity type into the polysilicon layer through the opening in the third mask, thereby to form a PN diode in the remaining portion of the polysilicon layer.

18. The method of claim 17 comprising depositing a metal layer in contact with the surface of the semiconductor body and the remaining portion of the polysilicon layer.

20. The method of claim 19 comprising oxidizing an exposed surface of the polysilicon to form a third oxide layer at the top of the trench, the third oxide layer extending down into the trench and being thicker than the first oxide layer.

21. The method of claim 20 comprising introducing dopant of a first conductivity type into the semiconductor body to form a body region, a junction of the body region being at a level with an upper surface of the first oxide layer.

19. A process for fabricating a trench MOSFET comprising:

providing a semiconductor body having a surface;

forming a first mask over the surface, the first mask having an opening where a trench is to be located in the body;

etching the semiconductor material through the opening in the first mask to form a trench in the semiconductor body;

depositing an oxide in the trench;

etching the oxide to form a first oxide layer on a bottom of the trench;

forming a second oxide layer on a sidewall of the trench, the first oxide layer being thicker than the second oxide layer; and

introducing polysilicon into the trench.

22. A trench-gated power MOSFET comprising;

a semiconductor body having a trench formed therein, a wall of the trench intersecting a major surface of the semiconductor body at a trench corner, the semiconductor body comprising;

a source region of a first conductivity type adjacent the trench and the major surface of the body;

a body region of a second conductivity type forming a junction with the source region, the body region comprising a channel region adjacent the wall of the trench; and

a drain region of the first conductivity type forming a junction with the body region; and

a gate disposed in the trench, the gate being bordered by a gate oxide layer, the gate oxide layer comprising a first portion adjacent the channel region and a second portion overlying the gate, the second portion being thicker than the first portion; and

a metal layer in contact with the top surface of the semiconductor body, the contact between the metal layer and the top surface extending laterally to the trench corner.

23. The trench-gated power MOSFET of claim 22 wherein a lower surface of the second portion of the gate oxide layer is below a level of the surface of the semiconductor body.

24. The trench-gated power MOSFET of claim 23 wherein an upper surface of the second portion of the gate oxide layer is above the level of the surface of the semiconductor body.

25. The trench-gated power MOSFET of claim 22 wherein the gate oxide layer comprises a third portion adjacent a bottom of the trench, the third portion being thicker than the first portion.

26. The trench-gated power MOSFET of claim 25 wherein an upper surface of the third portion is at a level equal to the junction between the body region and the drain region.

28. The trench-gated power MOSFET of claim 27 wherein a lower surface of the second portion of the gate oxide layer is below a level of the surface of the semiconductor body.

29. The trench-gated power MOSFET of claim 28 wherein an upper surface of the second portion of the gate oxide layer is above the level of the surface of the semiconductor body.

30. The trench-gated power MOSFET of claim 27 wherein the gate oxide layer comprises a third portion adjacent a bottom of the trench, the third portion being thicker than the first portion.

31. The trench-gated power MOSFET of claim 30 wherein an upper surface of the third portion is at a level equal to the junction between the body region and the drain region.

27. A trench-gated power MOSFET comprising;

a semiconductor body having a major surface and a trench formed in the semiconductor body, the semiconductor body comprising;

a source region of a first conductivity type adjacent the trench and the major surface of the body;

a body region of a second conductivity type forming a junction with the source region, the body region comprising a channel region adjacent the wall of the trench; and

a drain region of the first conductivity type forming a junction with the body region; and

a gate disposed in the trench, the gate being bordered by a gate oxide layer, the gate oxide layer comprising a first portion adjacent the channel region and a second portion overlying the gate, the second portion being thicker than the first portion, the second portion not overlapping the major surface of the semiconductor body outside the trench; and

a metal layer in contact with the top surface of the semiconductor body.

32. A trench-gated power MOSFET comprising;

a semiconductor body having a major surface and a trench formed in the semiconductor body, the semiconductor body comprising;

a source region of a first conductivity type adjacent the trench and the major surface of the body;

a body region of a second conductivity type forming a junction with the source region, the body region comprising a channel region adjacent the wall of the trench; and

a drain region of the first conductivity type forming a junction with the body region; and

a gate disposed in the trench, the gate being bordered by a gate oxide layer, the gate oxide layer comprising a first portion adjacent the channel region and a second portion at a bottom of the trench, the second portion being thicker than the first portion.

33. The trench-gated power MOSFET of claim 32 wherein an upper surface of the second portion is at a level equal to the junction between the body region and the drain region.

35. The method of claim 34 wherein depositing the metal layer is performed at a pressure of about two atmospheric pressures.

36. The method of claim 34 further comprising depositing a barrier layer on a surface of the mesa.

38. The method of claim 37 wherein forming a second insulating layer comprises forming a glass layer.

39. The method of claim 37 wherein depositing a first metal layer comprises depositing a metal from the group consisting of tungsten and copper.

40. The method of claim 37 wherein planarizing the first metal layer comprises chemical-mechanical polishing.

41. The method of claim 37 wherein planarizing the first metal layer comprises etching.

42. The method of claim 37 wherein forming a gate in the trench comprises depositing a polysilicon layer.

43. The method of claim 42 further comprising oxidizing the polysilicon layer to form a top oxide layer overlying a remaining portion of the polysilicon layer.

34. A method of fabricating a MOSFET comprising:

providing a semiconductor body;

forming a trench in a surface of the semiconductor body, the trench defining a mesa;

forming a first insulating layer along a wall of the trench;

forming a gate in the trench, the gate being insulated from the semiconductor body by the insulating layer;

implanting dopant of a first conductivity type into the mesa to form a body region;

implanting dopant of a second conductivity type into the mesa to form a source region;

forming a second insulating layer over the mesa;

etching an opening in the second insulating layer; and

depositing a metal layer into the contact opening to form an electrical contact with the source region, the depositing being performed at a pressure greater than atmospheric pressure.

37. A method of fabricating a MOSFET comprising:

providing a semiconductor body;

forming a trench in a surface of the semiconductor body, the trench defining a mesa;

forming a first insulating layer along a wall of the trench;

forming a gate in the trench, the gate being insulated from the semiconductor body by the insulating layer;

implanting dopant of a first conductivity type into the mesa to form a body region;

implanting dopant of a second conductivity type into the mesa to form a source region;

forming a second insulating layer over the mesa;

etching an opening in the second insulating layer;

depositing a first metal layer into the contact opening to form an electrical contact with the source region;

planarizing the first metal layer to form a plug, a surface of the plug being coplanar with a surface of the second insulating layer; and

depositing a second metal layer over the second insulating layer and the plug.