Packet-data processing apparatus

• US 20020019882A1
• Filed: 03/27/2001
• Published: 02/14/2002
• Est. Priority Date: 08/09/2000
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tsuruoka, Tetsumei, Kojima, Yuji, Umezaki, Yasuyuki, Shimozono, Yoshitomo, Soejima, Satoshi
• Granted Patent: US 6,654,823 B2
• Time in Patent Office: Days
• US Class Current: 709/249
• CPC Class Codes: H04L 12/4633 Interconnection of networks using encapsulation techniques, e.g. tunneling

Abstract

A packet-data-processing apparatus includes a first data-processing unit for computing information on a processing count; a memory; a second data-processing-unit for processing the input packet and storing first results in the memory; an access mechanism unit for reading out one of the first results written into the memory least recently from the memory at a request for a read operation and deleting the result of processing read out from the memory; a third data-processing unit for making the request for a read operation and carrying out processing based on the first result read out by the access control unit at the request and an input packet associated with the result of processing; and fourth data-processing unit constituting pipeline data-processing mechanism with said first and third data-processing unit.

Claims

1. A packet-data-processing apparatus for processing data of an input packet, said packet-data-processing apparatus comprising:

a first data-processing unit for computing information on a processing count based on the length of said input packet and outputting said information;

a memory;

a second data-processing unit for carrying out processing on pieces of data included in said input packet sequentially in accordance with said information on a processing count and storing a first result of processing at the end of said processing carried out on each of said pieces of data in said memory;

an access control unit for reading out one of said first results of processing written into said memory least recently from said memory at a request for a read operation and deleting said first result of processing read out from said memory from said memory;

a third data-processing unit for making said request for a read operation at reception of data at a predetermined position of said input packet by said third data-processing unit and carrying out processing based on said received input packet and said first result of processing read out by said access mechanism unit at said request; and

a fourth data-processing unit constituting pipeline data-processing mechanism with said first and third data-processing unit and having latency longer than latency which said second data-processing unit needs to store said first result of processing for said packet with a greatest packet length packet into said memory, wherein said memory provides a sufficient storage area for storing a first result of processing for an input packet having the longest latency since the first result of processing is generated till the first result of processing is supplied to said third data-processing unit.

2. A packet-data-processing apparatus according to claim 1 wherein:

said apparatus further includes a fifth data-processing unit for carrying processing based on packet data set in a fixed-length field of an input packet and outputting a second result of processing; and

said third data-processing unit carries out processing based on said first results of processing, said second result of processing and said input packet.

3. A packet-data-processing apparatus according to claim 2 wherein:

a first set of shift registers connected to each other in cascade is provided for each of said second to fifth data-processing units; and

said second to fifth data-processing units each carry out processing based on said packet stored in said respective set of shift registers.

4. A packet-data-processing apparatus according to claim 2 wherein:

a set of shift registers connected to each other in cascade is provided for each of said third to fifth data-processing units;

said second data-processing unit is provided in parallel to said set of shift registers; and

said third and fifth data-processing units each carry out processing based on said packet stored in said respective set of shift registers.

5. A packet-data-processing apparatus according to claim 3, said apparatus further including a second set of shift registers each for storing intermediate data related to said packet wherein said second set of shift registers is provided in parallel to said first set of shift registers.