FIELD PROGRAMMABLE PROCESSOR USING DEDICATED ARITHMETIC FIXED FUNCTION PROCESSING ELEMENTS

• US 20020019925A1
• Filed: 12/04/1998
• Published: 02/14/2002
• Est. Priority Date: 06/07/1996
• Status: Active Grant

• Current Assignee: Systolix Limited
• Original Assignee: Systolix Limited
• Inventors: DEWHURST, ANDREW, WORK, GORDEN
• Granted Patent: US 6,449,708 B2
• Time in Patent Office: Days
• US Class Current: 712/9
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A field programmable processor comprises a regular array of processing elements each of which is adapted to perform a fixed arithmetic function on packets of data. The processing elements are interconnected by an array of signal conductors extending adjacent the processing elements. Switching means are provided for selectively connecting the processing elements to the adjacent signal conductors so as to interconnect the processing elements. Program data representing desired processing element interconnections is stored, the switching means is controlled in accordance with the stored program data to achieve the desired processing element interconnections. The packets of data are transmitted between the interconnected processing elements.

Claims

1. A field programmable processor comprising a regular array of processing elements each of which is adapted to perform a fixed function on packets of data, an array of signal conductors extending adjacent the processing elements, switching means for selectively connecting the processing elements to the adjacent signal conductors so as to interconnect the processing elements, means for storing program data representing desired processing element interconnections, means for controlling the switching means in accordance with the stored program data to achieve the desired processing element interconnections, means for storing numeric data values within each processing element, and means for synchronously transmitting packets of data between the interconnected processing elements, characterised in that the interconnections between processing elements remain fixed once the processor has been programmed and, wherein the packets of data are synchronously transmitted between the processing elements in serial form.

2. A processor according to claim 1, comprising a further array of signal conductors extending adjacent the processing elements, the further array being arranged to convey function control data between the processing elements.

3. A processor according to claim 2, wherein the function control data is generated by a processing element or a combination of processing elements.

4. A processor according to claim 2 or 3, wherein the function controlled by the function control data is any one of reset, set, enable or modification of the signal data.

5. A processor according to any preceding claim, wherein the function of each processing element is either multiply or add.

6. A processor according to claim 5, wherein at least one processing element having the multiply function uses a synchronous shift and add operation.

7. A processor according to any preceding claim, wherein the processing elements are arranged in an array of identical groups of elements, each group incorporating processing elements of different functions.

8. A processor according to claim 7, wherein each identical group comprises one processing element with the add function and three processing element having the multiply function.

9. A processor according to any preceding claim, wherein the processor element has delay means so that data on an output of the processing element is a copy of the input data delayed by the time it takes to transmit a complete packet of data.

10. A processor according to any preceding claim, comprising means to transmit control data between the further array of signal conductors and an external control data source or destination.

11. A processor according to any preceding claim, wherein means are provided for converting the stored numeric data value into serial format so that it may be used in the processing element.

12. A processor according to any preceding claim, wherein said data packets contain control flags.

13. A processor according to claim 12, wherein data packets passed between processing elements include control flags indicating errors resulting from arithmetic operations in the processing element from which data is transmitted, and means are provided for correcting errors in data received by at least some of the processing elements.

14. A processor according to claim 13, wherein the processing elements perform arithmetic operations using fixed point processes, and the errors indicated by the control data are positive and/or negative overflow.

15. A processor according to claim 13 or 14, comprising multiplier processing elements which incorporate means for handling locally generated errors.

16. A processor according to any preceding claim, comprising analogue to digital and digital to analogue converters connected to the signal conductors to enable digital conversions of input analogue signals to be delivered to the processing elements and to enable the output of analogue conventions of digital signals produced by the processing elements.

17. A field programmable processor comprising a regular array of processing elements, an array of signal conductors extending adjacent the elements, switching means for selectively connecting the elements to the adjacent signal conductors so as to interconnect the elements, means for storing program data representing desired element interconnections, means for controlling the switching means in accordance with the stored program data to achieve the desired processing element interconnections, means for transmitting packets of data between the interconnected elements, and means for handling errors appearing in the output of one element in a subsequent element.