High accuracy timing model for integrated circuit verification
First Claim
1. A computer implemented method for determining timing delay for a circuit in an integrated circuit, said method comprising the steps of:
- determining a resistive-capacitive (“
RC”
) network between a driving point and a receiving point, said circuit driving said RC network at said driving point;
storing a circuit characterization model for said circuit, said circuit characterization model depicting relationships among input signal slew rate, load capacitance, current at said driving point and voltage at said driving point for said circuit;
determining a plurality of effective driving currents for said circuit at said driving point based on said circuit characterization model; and
determining timing delay parameters from said effective driving currents.
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Accused Products
Abstract
A variable current source model accurately determines timing delays for designs of circuits implemented in integrated circuits. A design for an integrated circuit specifies a resistive-capacitive (“RC”) network. The RC network couples a driving point and a receiving point, and a circuit specified in the design, drives the RC network at the driving point. The variable current source model determines driving currents for the circuit at the driving point based on the RC network and a characterization model of the circuit. A timing delay between the driving point and the receiving point is determined by simulating the drive of the RC network with the driving current at the driving point.
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Citations
25 Claims
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1. A computer implemented method for determining timing delay for a circuit in an integrated circuit, said method comprising the steps of:
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determining a resistive-capacitive (“
RC”
) network between a driving point and a receiving point, said circuit driving said RC network at said driving point;
storing a circuit characterization model for said circuit, said circuit characterization model depicting relationships among input signal slew rate, load capacitance, current at said driving point and voltage at said driving point for said circuit;
determining a plurality of effective driving currents for said circuit at said driving point based on said circuit characterization model; and
determining timing delay parameters from said effective driving currents. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for characterizing a circuit for determining a timing delay, said method comprising the step of:
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determining a resistive-capacitive (“
RC”
) network between a driving point and a receiving point, said circuit driving said RC network at said driving point;
selecting a plurality of time instances for analysis of said circuit;
determining a load capacitance for each of said time instances, said load capacitance specifying a capacitance from said driving point of said circuit;
determining operation of said circuit at a new time instance based on said load capacitance of a previous time instance; and
determining timing delay parameters based on operation of said circuit and response to said RC network at said time instances. - View Dependent Claims (11, 12, 14, 15, 16, 17, 18, 19, 20, 21)
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13. A computer readable medium, comprising a plurality of instructions, which when executed by a computer, causes the computer to determine timing delays for a circuit in an integrated circuit, said instructions for:
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determining a resistive-capacitive (“
RC”
) network between a driving point and a receiving point, said circuit driving said RC network at said driving point;
storing a circuit characterization model for said circuit, said circuit characterization model depicting relationships among input signal slew rate, load capacitance, current at said driving point and voltage at said driving point for said circuit;
determining a plurality of effective driving currents for said circuit at said driving point based on said circuit characterization model; and
determining timing delay parameters from said effective driving currents.
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22. A computer readable medium, comprising a plurality of instructions, which when executed by a computer, causes the computer to determine timing delays for a circuit in an integrated circuit, said instructions for:
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determining a resistive-capacitive (“
RC”
) network between a driving point and a receiving point, said circuit driving said RC network at said driving point;
selecting a plurality of time instances for analysis of said circuit;
determining a load capacitance for each of said time instances, said load capacitance specifying a capacitance from said driving point of said circuit;
determining operation of said circuit at a new time instance based on said load capacitance of a previous time instance; and
determining timing delay parameters based on operation of said circuit and response to said RC network at said time instances. - View Dependent Claims (23, 24)
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25. A computer implemented method for determining timing delay for a circuit in an integrated circuit, said method comprising the steps of:
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determining a resistive-capacitive (“
RC”
) network between a driving point and a receiving point, said circuit driving said RC network at said driving point;
storing a circuit characterization model for said circuit, said circuit characterization model depicting relationships among input signal slew rate, load capacitance, current at said driving point and voltage at said driving point for said circuit;
selecting a plurality of time instances;
selecting an initial drive current;
determining a drive voltage for each of said time instances, corresponding to said drive current, by simulating the drive, at said driving point, of said RC network with said initial drive current;
determining an effective capacitance for each of said time instances as a load for said circuit;
determining a new drive current for each of said time instances for said circuit from said drive voltage and said effective capacitance of a previous time instance;
repeating the steps of determining a drive voltage and determining an effective capacitance for said plurality of drive currents at each of said time instances;
determining a voltage at said receiving point from a transfer function of said RC network;
determining timing parameters for RC network propagation delay from said voltage at said driving point and said voltage at said receiving point;
receiving an input voltage to said circuit;
determining a voltage at said driving point from an impedance of said RC network and said driving currents; and
determining timing parameters for driving instance delay of said circuit from said input voltage to said voltage at said driving point.
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Specification