Method of preventing semiconductor layers from bending and seminconductor device formed thereby

• US 20020022308A1
• Filed: 05/18/2001
• Published: 02/21/2002
• Est. Priority Date: 08/17/2000
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ahn, Dong-Ho, Kang, Ho-Kyu, Bae, Geum-Jong
• Granted Patent: US 6,881,645 B2
• Time in Patent Office: Days
• US Class Current: 438/164
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form
• CPC Class Codes: H01L 21/76235 trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.

Claims

1. A method for preventing bending of a patterned SOI layer during trench sidewall oxidation, the method comprising:

providing a patterned SOI layer having at least one trench, said patterned SOIL layer disposed upon an underlying buried silicon oxide layer; and

blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.

2. The method of claim 1 wherein said step of blocking oxygen diffusion comprises providing a nitrogen-containing layer between said patterned SOI and buried silicon oxide layers.

3. The method of claim 1, wherein the nitrogen-containing layer is formed by implanting nitrogen ions.

4. The method of claim 3, wherein the nitrogen ions are implanted after forming a pad oxide layer on a surface of the SOI layer.

5. A method for preventing a bending phenomenon of a silicon on insulator (SOI) layer, the method comprising:

etching an SOI layer of an SOI-type substrate comprising a buried oxide silicon layer, and an SOI layer to form a trench; and

tilting the SOI-type substrate where the trench is formed and implanting nitrogen ions thereinto, forming a nitrogen-containing layer between the SOI layer and the buried oxide silicon layer at an area adjacent to the trench.

6. A method for preventing a bending phenomenon of a silicon on insulator (SOI) layer, the method comprising:

forming a trench in an SOI layer of an SOI-type substrate; and

forming a single crystalline silicon layer on a sidewall of the trench.

7. The method of claim 6, wherein the said forming of a trench comprises:

stacking an etch-stop layer on the SOI-type substrate, and forming a pattern exposing a trench area; and

etching the SOI layer of the SOI-type substrate, using the pattern as an etching mask, to form a trench, and

wherein the step of forming the single crystalline silicon layer comprises;

conformally stacking an amorphous silicon layer on an overall surface of the SOI-type substrate including the trench;

annealing the SOI-type substrate to achieve solid phase epitaxial growth (SPE) at the amorphous silicon layer contacted with a sidewall of the trench;

stacking a buried oxide layer to fill the trench; and

performing a planarization etching process to remove the buried oxide layer over an active region.

8. The method of claim 7, wherein the annealing is carried out before stacking the buried oxide layer.

9. The method of claim 7, wherein the annealing is carried out in a nitrogen ambient at a temperature of 550-700°

C.

10. The method of claim 7, wherein the annealing is carried out in an ultra high vacuum (UHV) system.

11. The method of claim 8, wherein a sidewall oxidation process follows before stacking the buried oxide layer, forming an oxide layer on a surface of the amorphous silicon layer.

12. The method of claim 7, wherein the annealing is carried out after stacking the amorphous silicon layer in the trench, forming an oxide layer on the surface of the amorphous silicon layer, and filling the trench with a buried oxide layer.

13. The method of claim 12, wherein the annealing is carried out to the buried oxide layer.

14. The method of claim 12, wherein the annealing is carried out at a temperature of 750-1150°

C. for an hour.

16. The method of claim 15, wherein the step of conformally stacking the CVD oxide layer is performed at a lower pressure to a thickness of 50-500 Å

.

17. The method of claim 15, after the step of conformally stacking the CVD oxide layer, further comprising:

forming a silicon nitride liner; and

filling the trench will a buried oxide layer.

19. The method of claim 18, wherein the RTO is performed at a temperature of 950-1180°

C. for 30-200 seconds.

20. The method of claim 18, after the step of forming the thermal oxide layer, further comprising:

forming a silicon nitride liner; and

filling the trench with a buried oxide layer.

15. A method for preventing a bending phenomenon of a silicon on insulator (SOI) layer, the method comprising:

etching an SOI layer of an SOI-type substrate comprising a buried silicon oxide layer, and the SOI layer, forming a trench; and

conformally stacking a CVD oxide layer on an overall surface of the SOI-type substrate including the trench.

18. A method for preventing a bending phenomenon of a silicon on insulator (SOI) layer, the method comprising:

etching an SOI layer of an SOI-type substrate including a lower silicon layer, a buried silicon oxide layer, and the SOI layer, forming a trench; and

performing rapid thermal oxidation (RTO) to the trench, forming a thermal oxide layer.

21. A trench device isolation type semiconductor device having a buried silicon oxide layer, and a silicon on insulator (SOI) layer in an active region, comprising:

a nitrogen-containing layer formed between the buried silicon oxide layer and the SOI layer, around at least the active region.

22. The device of claim 21, wherein a trench device isolation layer includes an oxide layer at a side contacted with the active region.

23. The device of claim 22, wherein the oxide layer is made of one selected from the group consisting of thermal oxide, CVD oxide, and oxide created by rapid thermal oxidation (RTP) technique.

24. The device of claim 22 further comprising a silicon nitride liner at the opposite side of the substrate on the basis of the oxide layer.

26. The device of claim 25 further comprising a thermal oxide layer at the opposite side of the active region on the basis of the single crystalline silicon layer.

27. The device of claim 26 farther comprising a silicon nitride liner at the opposite side of the single crystalline silicon layer on the basis of the thermal oxide layer.

30. The method of claim 29, wherein the nitrogen-containing layer is formed by implanting nitrogen ions in the step of forming the SOI-type substrate.

31. The method of claim 30, wherein the nitrogen ions are implanted in a state of forming a pad oxide layer on a surface of the SOI layer.

25. A trench device isolation type semiconductor device, comprising:

a buried silicon oxide layer and a silicon on insulator (SOI) layer in an active region;

a single crystalline silicon layer formed by solid phase epitaxial growth (SPE) of a sidewall of the active region contacted with a device isolation layer of the trench.

28. A trench device isolation type semiconductor device having a buried silicon oxide layer, and a silicon-on-insulator (SOI) layer in an active region, comprising:

means for blocking the diffusion of oxygen between said SOI layer and said buried silicon oxide layer.

29. A method for preventing a bending phenomenon of a silicon on insulator (SOI) layer, the method comprising the steps of:

forming a SOI-type substrate including a lower silicon layer, a buried oxide silicon layer, a SOI layer, and a nitrogen-containing layer between the buried oxide silicon layer and the SOI layer; and

etching the SOI layer of the SOI-type substrate to form a trench for device isolation.

32. A method for preventing a bending phenomenon of a silicon on insulator (SOI) layer, the method comprising the steps of:

etching a SOI layer of a SOI-type substrate including a lower silicon layer, a buried oxide silicon layer, and a SOI layer to form a trench; and

tilting the SOI-type substrate where the trench is formed and implanting nitrogen ions thereinto, forming a nitrogen-containing layer between the SOI layer and the buried oxide silicon layer at an area adjacent to the trench.