System for transmitting information codes with multi-level modulation scheme and a modulation apparatus

• US 20020023247A1
• Filed: 08/16/2001
• Published: 02/21/2002
• Est. Priority Date: 08/21/2000
• Status: Abandoned Application

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Akiyama, Toshiyuki, Kokuryo, Yoshiro
• Application Number:
  US09/930,230
• Publication Number:
  US 20020023247A1
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 27/3416 in which the information is carried by both the individual signal points and the subset to which the individual points belong, e.g. using coset coding, lattice coding, or related schemes

Abstract

A transmission system for transmitting information codes by using a multi-level modulation scheme has a transmitter and a receiver. The transmitter has a divider circuit for dividing inputted N-bit information data stream into M (M is integer not less than 2) data stream; an error correction coding circuit for individually converting the M streams into error correcting code streams so as to deliver M error correcting code streams; a multi-level modulation circuit for making the correspondence between data streams of N bits constituted by the M error correcting code streams and a plurality of signal points arranged on a signal constellation and modulating two carriers with coordinate values of signal points on the signal constellation corresponding to the N-bit code stream; and a high frequency circuit unit for outputting a modulated signal in a radio frequency to a transmission antenna.

Claims

1. A transmission system for transmitting information codes by using a multi-level modulation scheme, comprising a transmitter and a receiver for receiving a transmission signal from said transmitter, said transmitter including:

a divider circuit for inputting information data stream and dividing said information data stream into M data streams, wherein M is an integer not less than 2;

an error correction coding circuit for individually converting said M data streams into error correcting coded data stream so as to deliver M error correcting coded data streams;

a multi-level modulation circuit for making the correspondence between data stream of N bits, wherein N is an integer not less than 2, constituted by said M error correcting coded data streams and a plurality of signal points arranged on a signal constellation and modulating two carriers orthogonal to each other with coordinate values of signal points on the signal constellation corresponding to said N-bit coded data stream; and

a high frequency circuit unit for converting a modulated signal delivered out of said multi-level modulation circuit into a radio frequency and delivering it to a transmission antenna.

2. A transmission system according to claim 1, wherein said divider circuit divides said inputted information data stream into first and second data streams;

said error correction coding circuit includes;

a first error correction coding circuit for converting said first data stream into a first error correcting coded data stream;

a first serial/parallel conversion circuit for rearranging said first error correcting coded data stream to a word of n bits, where n is an integer not less than 2, and delivering a first word stream;

a second error correction coding circuit for converting said second data stream into a second error correcting coded data stream; and

a second serial/parallel conversion circuit for rearranging said second error correcting coded data stream to a word of m bits, where m is not less than 2, and delivering a second word stream, and

said multi-level modulation circuit is based on a multi-level signal modulation scheme in which word of (m+n) bits are made to correspond to 2^(m+n) signal points arranged on said signal constellation, said word of (m+n) bits are multi-level signals including word of n bits, of which at least one bit has a word value different from that of the other between the most adjacent signal points, and the remaining word of m bits and said multi-level signals are modulated, whereby two carriers orthogonal with each other are modulated with coordinate component values of signal points on the signal constellation corresponding to the word of (m+n) bits constituted by n bits of said first word stream and m bits of said second word stream and the modulated two carriers are synthesized to deliver a modulated signal to said high frequency circuit unit.

3. A transmission system according to claim 2, wherein said multi-level modulation circuit forms the multi-level signals based on 2^(m+n)-QAM modulation scheme by:

arranging 2^(m+n) signal points constituted by an arrangement of 2^m blocks each having 2ⁿ signal points on said signal constellation;

assigning, in each block, 2^m different word of m bits and 2ⁿ different word of n bits in gray code configuration to 2^(m+n) signal points, said word of m bits being for specifying a block to which signal points said word correspond to belong and said word of n bits being for specifying positions in the block to which said signal points said word correspond to belong; and

assigning word of (m+n) bits resulting from combining said m-bit word and said n-bit word to said 2^(m+n) signal points on said signal constellation.

4. A transmission system according to claim 2, wherein each of said first error correction coding circuit and said second error correction coding circuit is a convolution coding circuit, and the value of code rate in said second error correction coding circuit is set to be larger than that in said first error correction coding circuit.

5. A transmission system according to claim 1, wherein said receiver includes:

a received signal point calculating circuit for calculating coordinate values of received signals on the signal constellation;

a first error correction decoding unit for selecting a signal point closest to a calculated coordinate value of a received signal from signal points arranged on said signal constellation, determining a received first error correcting coded data stream corresponding to n bits of a first word stream within a word of (m+n) bits corresponding to the selected signal point, and reproducing a received first data stream by decoding said received first error correcting coded data stream;

a first delay circuit for delaying said received first data stream reproduced by said first error correction decoding unit by a predetermined time and delivering the delayed data stream;

a re-correction coding unit for converting said received first data stream reproduced by said first error correction decoding unit into said received first error correcting data stream;

a second delay circuit for delaying a coordinate value of said received signal calculated by said received signal point calculating circuit by a predetermined time and delivering the delayed coordinate value;

a second error correction decoding unit for inputting the output of said second delay circuit and the output of said re-correction coding unit, selecting a signal point closest to the coordinate value of the inputted received signal from the signal points arranged on said signal constellation, determining a received second error correcting code data stream corresponding to m bits of a second word stream within a code of (m+n) bits corresponding to the selected signal point, and reproducing a received second data stream by decoding said received second error correcting coded data stream; and

a data stream combining circuit for combining said received first data stream delivered out of said first delay circuit and said received second data stream delivered out of said second error correction decoding unit and delivering a combined data stream as reproduced information data stream.

6. A transmission system according to claim 1, wherein said receiver includes:

a received signal point calculating circuit for calculating coordinated values of received signals on the signal constellation;

a first signal point position deciding circuit for selecting a signal point closest to a calculated coordinate value of a received signal from signal points arranged on said signal constellation, calculating a code corresponding to n bits of a first word stream within a word of (m+n) bits corresponding to the selected signal point and delivering the calculated code as a received first word stream;

a first parallel/serial conversion circuit for converting the received first word stream delivered out of said first signal point position deciding circuit into a serial code so as to deliver a received first error correcting code stream;

a first error correction decoding circuit for decoding said received first error correcting coded data stream from said first parallel/serial conversion circuit to reproduce a received first data stream;

a first delay circuit for delaying said received first data stream reproduced by said first error correction decoding circuit by a predetermined time;

a received first error correction coding circuit for converting said received first data stream reproduced by said first error correction decoding circuit into a received first error correcting coded data stream;

a first serial/parallel conversion circuit on the receiving side for converting said received first error correcting coded data stream into a parallel code of one word stream of n bits at the same timing as that for the conversion process in said first parallel/serial conversion circuit and delivering the parallel code;

a second delay circuit for delaying the coordinate value of said received signal calculated by said received signal point calculating circuit by a predetermined time and delivering the delayed value;

a second signal point position deciding circuit for inputting the output of said second delay circuit and the output of said first serial/parallel conversion circuit on the receiving side, selecting a signal point closest to the inputted coordinate value of received signal from signal points arranged on said signal constellation, calculating a code corresponding to m bits of a received second word stream within a word of (m+n) bits corresponding to the selected signal point, and delivering the calculated code as the received second word stream;

a second parallel/serial conversion circuit for converting said received second word stream delivered out of said second signal point position deciding circuit into a serial code so as to deliver a received second error correcting coded data stream;

a second error correction decoding circuit for decoding said received second error correcting coded data stream from said second parallel/serial conversion circuit so as to reproduce and deliver a received second data stream; and

a data stream combining circuit for combining said received first data stream delivered out of said first delay circuit and said received second data stream delivered out of said second error correction decoding circuit and delivering a combined data stream as reproduced information data stream.

7. A transmission system according to claim 6, wherein said first error correction decoding circuit includes a first Viterbi decoding circuit for carrying out soft decision Viterbi decoding, and said second error correction decoding circuit includes a second decoding circuit for carrying out hard decision Viterbi decoding.

8. A transmission system according to claim 6, wherein each of said first error correction decoding circuit and said second error correction decoding circuit includes a Viterbi decoding circuit for carrying out soft decision Viterbi decoding.

9. A transmission system according to any of claims 2 to 8, wherein said first serial/parallel conversion circuit has a bit interleave circuit for applying a bit interleave process to the code resulting from rearrangement of said first error correction coded data stream to the word of n bits and delivering said first word stream.

10. A modulation apparatus used for a transmission system for transmitting information data stream by using a multi-level modulation scheme, comprising:

a divider circuit for inputting information data stream and dividing said information data stream into M data streams, where M is an integer not less than 2;

an error correction coding circuit for individually converting said M data streams into error correcting coded data stream and delivering M error correcting data stream; and

a multi-level modulation circuit for making the correspondence between data streams of N bits constructed of said M error correcting data streams and a plurality of signal points arranged on a signal constellation and modulating two carriers orthogonal with each other with coordinate values of signal points on the signal constellation corresponding to the N-bit data stream.

11. A modulation apparatus according to claim 10, wherein said divider circuit divides said inputted N-bit information data stream into first and second data streams;

said error correction coding circuit includes;

a first error correction coding circuit for converting said first data stream into a first error correcting code data stream;

a first serial/parallel conversion circuit for rearranging said first error correcting coded data stream to a word of n bits, where n is an integer not less than 2, and delivering a first word stream;

a second error correction coding circuit for converting said second data stream into a second error correcting code data stream; and

a second serial/parallel conversion circuit for rearranging said second error correcting data stream to a word of m bits, where m is an integer not less than 2, and delivering a second word stream, and said multi-level modulation circuit is based on a multi-level signal modulation scheme in which word of (m+n) bits are made to correspond to 2^(m+n) signal points arranged on said signal constellation, said wird if (m+n) bits are multi-level signals including word of n bits, of which at least one has a word value different from that of the other between the most adjacent signal points, and the remaining word of m bits and said multi-level signals are modulated, whereby two carriers orthogonal with each other are modulated with coordinate component values of signal points on the signal constellation corresponding the word of (m+n) bits constituted by n bits of said first word stream and m bits of said second word stream and are synthesized to deliver the modulated two carriers.

12. A modulation apparatus according to claim 11, wherein said multi-level modulation circuit forms multi-level signals based on a 2^(m+n)-QAM modulation scheme in such a manner that:

2^(m+n) signal points constituted by an arrangement of 2^m blocks each having 2ⁿ signal points are arranged on said signal constellation;

in each block, 2^m different codes of m bits and 2ⁿ different word of n bits in gray code configuration are assigned to 2^(m+n) signal points, said word of m bits being for specifying a block to which signal points said word correspond to belong and said word of n bits being for specifying positions in the block to which signal points said word correspond to belong; and

word of (m+n) bits obtained by combining said m-bit word and said n-bit word are assigned to said 2^(m+n) signal points on said signal constellation.