Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device

• US 20020024064A1
• Filed: 09/07/2001
• Published: 02/28/2002
• Est. Priority Date: 08/21/1997
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Ryuji Shibata, Shigeru Shimada
• Inventors: Shibata, Ryuji, Shimada, Shigeru
• Granted Patent: US 6,462,978 B2
• Time in Patent Office: Days
• US Class Current: 257/207
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user'"'"'s purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.

Claims

1. A semiconductor integrated circuit device comprising:

memory mats arranged in a first direction,

each of said memory mats including memory cells arranged in said first direction and a second direction, perpendicular to said first direction,

said memory cells being formed in a well region, formed in a substrate, respectively;

first power supply lines electrically connected to said memory cells and extending on said memory mats in said first direction; and

second power supply lines and third power supply lines extending over said first power supply lines in said second direction and arranged between adjacent ones of said memory mats, in said first direction,

said second power supply lines being electrically connected to said first power supply lines, and

said third power supply lines being electrically connected to said well region.

2. A semiconductor integrated circuit device according to claim 1,

wherein said second power supply lines and said third power supply lines extend over a word shunt area, and

wherein at said word shunt area said third power supply lines are electrically connected to said well region.

3. A semiconductor integrated circuit device according to claim 1, wherein switch circuits are placed at both of opposing ends of said memory mats, in said second direction, and are, respectively, electrically connected to corresponding ones of said third power supply lines through a transistor for supplying one of a first voltage and a second voltage, lower than said first voltage.

4. A semiconductor integrated circuit device according to claim 1, wherein ones of said second power supply lines are electrically connected to corresponding ones of said third power supply lines at outside said memory mats.

20. A semiconductor integrated circuit device according to claim 1,

wherein said first direction corresponds to a data line direction and said second direction corresponds to a word line direction of said memory mats, respectively, and

wherein each of said memory cells in at least one of said memory mats is a static random access memory cell including a cross-coupled CMOS latch circuit and a pair of transfer MISFETs which are coupled between input/output nodes of said latch circuit and a corresponding pair of complementary data lines, respectively.

21. A semiconductor integrated circuit device according to claim 20, wherein each word line is associated with a row of memory cells, each said row of memory cells in at least one of said memory mats is disposed such that in each memory cell N-channel MISFETs are provided in a p well region and p-channel MISFETs are provided in an n well region, the n well region and p well region associated with each memory cell in a row are disposed in parallel, and the n well regions and the p well regions of each said row are, respectively, disposed as an integrally formed N-well and an integrally formed P-well, both extended in said first direction.

22. A semiconductor integrated circuit device according to claim 21, wherein said N-well and said P-well associated with each row of memory cells, combinedly, overlie a similarly directioned buried well region, having one of a p and n-type conductivity, formed in said substrate, having the other of the p and n-type conductivity.

23. A semiconductor integrated circuit device according to claim 1, wherein said second and third power supply lines are disposed as plural sets each including a pair of adjacently disposed power supply lines and a pair of substrate potential supply lines, separated by said pair of power supply lines, and each set being disposed in a spacing between each adjacent pair of memory mats.

24. A semiconductor integrated circuit device according to claim 23, wherein each said spacing where a set of power supply and substrate potential supply lines are disposed constitutes a word shunt area of the device.

25. A semiconductor integrated circuit device according to claim 24, wherein said second and third power supply lines are formed at a same level, metal conductive layer.

26. A semiconductor integrated circuit device according to claim 25, wherein said first power supply lines are formed from a lower level conductive layer than that of said second and third power supply lines.

5. A semiconductor integrated circuit device comprising:

memory mats arranged in a first direction,

each of said memory mats including memory cells arranged in said first direction and a second direction, perpendicular to said first direction,

said memory cells being formed in a well region, formed in a substrate, respectively;

power supply lines extending in said second direction and arranged between adjacent ones of said memory mats in said first direction,

said power supply lines being electrically connected to said well region; and

switch circuits placed at both of opposing ends of said memory mats, in said second direction, and are, respectively, electrically connected to corresponding ones of said power supply lines through a transistor for supplying one of a first voltage and a second voltage, lower than said first voltage.

6. A semiconductor integrated circuit device according to claim 5, further comprising:

sense amplifying circuits each of which is arranged in said second direction between a corresponding one of said memory mats and a corresponding one of said switch circuits.

7. A semiconductor integrated circuit device according to claim 5,

wherein each of said power supply lines extends over a word shunt area, and

wherein at said word shunt area each of said power supply lines is electrically connected to said well region.

8. A semiconductor integrated circuit device according to claim 5, wherein said power supply lines are electrically connected to memory cell supply lines at outside said memory mats, said memory cell supply lines extend over said memory cells in said first direction.

9. A semiconductor integrated circuit device comprising:

memory mats arranged in a first direction,

each of said memory mats including memory cells arranged in said first direction and a second direction, perpendicular to said first direction,

said memory cells being formed in a well region, formed in a substrate, respectively;

first power supply lines electrically connected to said memory cells; and

second power supply lines and third power supply lines formed over said first power supply lines, extending in said second direction, and arranged between said adjacent memory mats in said first direction,

said second power supply lines being electrically connected to said first power supply lines, and

said third power supply lines being electrically connected to said well region.

10. A semiconductor integrated circuit device according to claim 9,

wherein said second power supply lines and said third power supply lines extend over a word shunt area, and

wherein at said word shunt area said third power supply lines are electrically connected to said well region.

11. A semiconductor integrated circuit device according to claim 9, wherein switch circuits are placed at both of opposing ends of said memory mats, in said second direction, and are, respectively, electrically connected to corresponding ones of said third power supply lines through a transistor for supplying one of a first voltage and a second voltage, lower than said first voltage.

12. A semiconductor integrated circuit device according to claim 9, wherein ones of said second power supply lines are electrically connected to corresponding ones of said third power supply lines at outside said memory mats.

14. A semiconductor integrated circuit device according to claim 13,

wherein said second power supply line and said third power supply line extend over a word shunt area, and

wherein at said word shunt area said third power supply line is electrically connected to said well region.

15. A semiconductor integrated circuit device according to claim 13, wherein switch circuits are placed at both of opposing ends of said first and second memory arrays, in said second direction, near said second and third power supply lines, and are electrically connected to said third power supply line through a transistor for supplying one of a first voltage and a second voltage, lower than said first voltage.

16. A semiconductor integrated circuit device according to claim 13, wherein said second power supply line is electrically connected to said third power supply line at outside said first and second memory mats.

18. A semiconductor integrated circuit device according to claim 17,

wherein said second power supply lines and said third power supply lines extend over a word shunt area, and

wherein at said word shunt area said third power supply lines are electrically connected to said well region.

19. A semiconductor integrated circuit device according to claim 17,

wherein switch circuits are placed at both of opposing ends of said memory mats, in said second direction, near said second and third power supply lines, and are electrically connected to corresponding ones of said third power supply lines through a transistor, and

wherein said second power supply lines are electrically connected to said third power supply lines at outside said switch circuits.

13. A semiconductor integrated circuit device comprising:

a first memory array and a second memory array arranged in a first direction,

each of the memory arrays including memory cells arranged in said first direction and in a second direction, perpendicular to said first direction,

said memory cells being formed in a well region, formed in a substrate, respectively;

a first power supply line electrically connected to said memory cells; and

a second power supply line and a third power supply line formed over said first power supply line, extending in said second direction, and arranged between said first memory array and said second memory array in said first direction,

said second power supply line being electrically connected to said first power supply line, and

said third power supply line being electrically connected to said well region.

17. A semiconductor integrated circuit device comprising:

memory mats arranged in a first direction,

each of said memory mats including memory cells arranged in said first direction and a second direction, perpendicular to said first direction,

said memory cells being formed in a well region, formed in a substrate, respectively;

first power supply lines electrically connected to said memory cells and extending on said memory mats in said first direction; and

second power supply lines and third power supply lines extending over said first power supply lines in said second direction and arranged between adjacent ones of said memory mats in said first direction,

said second power supply lines being electrically connected to said first power supply lines,

said third power supply lines being electrically connected to said well region, and

said second power supply lines being electrically connected to said third power supply lines at outside said memory mats.