Non-volatile passive matrix device and method for readout of the same

• US 20020024835A1
• Filed: 07/06/2001
• Published: 02/28/2002
• Est. Priority Date: 07/07/2000
• Status: Abandoned Application

• Current Assignee: Thin Film Electronics ASA
• Original Assignee: Thin Film Electronics ASA
• Inventors: Thompson, Michael O., Carlsson, Johan, Gustafsson, Goran, Womack, Richard
• Application Number:
  US09/899,096
• Publication Number:
  US 20020024835A1
• Time in Patent Office: Days
• US Class Current: 365/117
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

In a non-volatile passive matrix memory device comprising an electrically polarizable dielectric memory material exhibiting hysteresis between first and second sets of addressing electrodes, the electrodes of the first set are word lines and the electrodes of the second set are bit lines of the memory device. A memory cell with a capacitor-like structure is defined in the memory material at the overlap between a word line and a bit line. The word lines are divided into segments with each segments sharing and being defined by adjoining bit lines and means are provided for connecting each bit line of a segment with a sensing means, thus enabling simultaneous connections of all memory cells of a word line segment for readout via the bit lines of the segment. Each sensing means senses the charge flow in a bit line in order to determine a logical value stored in a memory cell defined by the bit line. In a readout method for a memory device of this kind a word line of a segment is activated according to a protocol by setting its potential to a switching voltage of the memory cell during at least a portion of a read cycle, while keeping the bit lines of the segment at zero potential, during which read cycle a logical value stored in the individual memory cells is sensed by the sensing means.

Use in a volumetric data storage apparatus with a plurality of stacked layers which each comprises a non-volatile passive matrix memory device.

Claims

1. A non-volatile passive matrix memory device (10) comprising an electrically polarizable dielectric memory material (12) exhibiting hysteresis, particularly a ferroelectric material, wherein said memory material (12) is provide sandwiched in a layer between a first set and second set of respective parallel addressing electrodes, the electrodes of the first set constituting word lines (WL) of the memory device and being provided in substantially orthogonal relationship to the electrodes of the second set, the latter constituting bit lines (BL) of the memory device, wherein a memory cell (13) with a capacitor-like structure is defined in the memory material (12) at crossing between word lines and bit lines, wherein the memory cells of the memory device constitute the elements of the passive matrix, wherein each memory cell can be selectively addressed for a write/read operation via a word line and bit line, wherein a write operation to a memory cell takes place by establishing a desired polarization state in the cell by means of a voltage being applied to the cell via the respective word line and bit line defining the cell, said applied voltage Vs either establishing a determined polarization state in the cell or being able to switch the cell between the polarization states thereof, and wherein a read operation takes place by applying a voltage smaller than the switching or polarization voltage Vs to the cell and detecting at least one electrical parameter of an output current on the bit lines, characterized in that

the word lines are divided into a number of segments, each segment sharing and being defined by a plurality of adjoining bit lines in the matrix, and that means (25) are provided for connecting each bit line assigned to a segment with an associated sensing means, thus enabling the simultaneous connection of all memory cells assigned to a word line on a segment for readout via the corresponding bit lines of the segment, each sensing means being adapted for sensing the charge flow in the associated bit line in order to determine a logical value stored in the memory cell defined by the bit line.

2. A non-volatile passive matrix memory device according to claim 1, characterized in that said means (25) for simultaneous connection of each bit line (BL_{1 . . . n}) of a segment (S_{1 . . . n}) with associated sensing means (SA_{1 . . . n}) during addressing are multiplexers.

3. A non-volatile passive matrix memory device according to claim 2, characterized in that the number of multiplexers corresponds to the largest number of bit lines (BL) defining a segment, each bit line of a segment being connected with a specific multiplexer.

4. A non-volatile passive matrix memory device according to claim 3, characterized in that the output of each multiplexer is connected with a single sensing means.

5. A non-volatile passive matrix memory device according to claim 4, characterized in that the single sensing means is a sense amplifier.

6. A non-volatile passive matrix memory device according to claim 1, characterized in that said means (25) for simultaneous connection of each bit line (BL_{1 . . . n}) of a segment (S_{1 . . . n}) to an associated sensing means (SA_{1 . . . n}) during addressing is a gate means.

7. A non-volatile passive matrix memory device according to claim 6, characterized in that all bit lines of a segment are connected with a specific gate means, each gate means having a number of outputs corresponding to the number of bit lines in the respective segment, that each output of each gate means is connected with a specific bus line of an output data bus, the number of bus lines thus corresponding to largest number of bit lines in a segment, and that each bus line is connected with a single sensing means.

8. A non-volatile passive matrix memory device according to claim 6, characterized in that the gate means (25) comprise pass gates.

9. A non-volatile passive matrix memory device according to claim 7, characterized in that the sensing means is a sense amplifier.

12. The use of a non-volatile passive matrix memory device according to claim 1 and a method for readout according to claim 10 in a volumetric data storage apparatus with a plurality of stacked layers, each layer comprising one of the non-volatile passive matrix memory devices.

10. A method for readout of a passive non-volatile matrix memory device comprising an electrically polarizable dielectric memory material (12) exhibiting hysteresis, particularly a ferroelectric material, wherein said memory material (12) is provided sandwiched in a layer between a first set and second set of respective parallel addressing electrodes, the electrodes of the first set constituting word lines (WL) of the memory device and being provided in substantially orthogonal relationship to the electrodes of the second set, the latter constituting bit lines (BL) of the memory device, wherein a memory cell (13) with a capacitor-like structure is defined in the memory material (12) at crossing between word lines and bit lines, wherein the memory cells of the memory device constitute the elements of the passive matrix, wherein each memory cell can be selectively addressed for a write/read operation via a word line and bit line, wherein write operation to a memory cell takes place by establishing a desired polarization state in the cell by means of a voltage being applied to the cell via the respective word line and bit line defining the cell, said applied voltage Vs either establishing a determined polarization state in the cell or being able to switch the cell between the polarization states thereof, wherein a read operation takes place by applying a voltage smaller than the switching or polarization voltage Vs to the cell and detecting at least one electrical parameter of an output current or the bit lines, wherein the method comprises steps for controlling electric potentials on all word lines and bit lines in a time-coordinated fashion according to a protocol comprising electric timing sequences for all word lines and bit lines,

arranging said protocol to comprise a read cycle, and

providing during the read cycle for sensing means to sense charges flowing in the bit lines, and wherein the method is characterized by connecting each bit line within a word line segment with an associated sensing means,

activating according to the protocol one word line of the segment at a time by setting the potential of said one word line of the segment to the switching voltage Vs during at least a portion of the read cycle, while keeping all bit lines of the segment at zero potential, and

determining the logical value stored in the individual cells sensed by the sensing means during the read cycle.

11. Method for readout according to claim 10, characterized by

connecting each bit line within a segment with an associated sensing means, keeping all word lines and bit lines, when no cell is read or written, at a quiescent voltage of approximately Vs/3,

activating according to the protocol one word line of the segment at a time by setting the potential of said one word line of the segment to the switching voltage Vs during at least a portion of the read cycle, while keeping all bit lines of the segment at zero potential, and

determining the logical value stored in the individual cells sensed by the sensing means during the read cycle.