Semiconductor integrated circuit and data processing system

• US 20020024846A1
• Filed: 11/01/2001
• Published: 02/28/2002
• Est. Priority Date: 09/30/1996
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Sato, Hiroshi, Noda, Satoshi, Yoshida, Keiichi, Kotani, Hiroaki, Kimura, Katsutaka, Kawahara, Takayuki, Kubono, Shoji, Nozoe, Atsushi
• Granted Patent: US 6,496,418 B2
• Time in Patent Office: Days
• US Class Current: 365/185.24
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

Claims

1. A semiconductor device comprising:

a memory array comprising nonvolatile memory cells;

a control circuit;

a setting circuit; and

a programming circuit,

wherein said control circuit controls program operation of said programming circuit for programming data to ones of said nonvolatile memory cells,

wherein said setting circuit is set therein with predetermined information for trimming of said program operation, and

wherein said programming circuit executes said program operation to ones of said nonvolatile memory cells according to said predetermined information in said setting circuit.

2. A semiconductor device according to claim 1,

wherein said programming circuit supplies program voltage pulses to said ones of said nonvolatile memory cells, and

wherein said programming circuit defines a minimum width of said program voltage pulses according to said predetermined information.

3. A semiconductor device according to claim 2,

wherein a width of one of said program voltage pulses is different from that of another one of said program voltage pulses, and

wherein said programming circuit defines a difference of width of said program voltage pulses according to said predetermined information.

4. A semiconductor device according to claim 3,

wherein said setting circuit comprises a plurality of fuse circuits, and

wherein said predetermined information is stored in said plurality of fuse circuits.

5. A semiconductor device according to claim 1,

wherein said programming circuit supplies program voltage pulses to said ones of said nonvolatile memory cells, and

wherein said programming circuit defines a minimum voltage of said program voltage pulses according to said predetermined information.

6. A semiconductor device according to claim 5,

wherein a voltage of one of said program voltage pulses is different from that of another one of said program voltage pulses, and

wherein said programming circuit defines a difference of voltage of said program voltage pulses according to said predetermined information.

7. A semiconductor device according to claim 6,

wherein said setting circuit comprises a plurality of fuse circuits, and

wherein said predetermined information is stored in said plurality of fuse circuits.

8. A nonvolatile memory device comprising:

a nonvolatile memory array comprising nonvolatile memory cells;

a control circuit;

a setting circuit; and

a programming circuit,

wherein said control circuit controls program operation of said programming circuit to program data to ones of said nonvolatile memory cells,

wherein said setting circuit is set therein with trimming information for trimming of said program operation,

wherein said programming circuit supplies to said ones of said nonvolatile memory cells a plurality of program voltage pulses according to said trimming information, and

wherein said trimming information is set into said setting circuit in an inspection process in a wafer process.

9. A nonvolatile memory device according to claim 8,

wherein said trimming information is used for trimming one of (1) a minimum width of said program voltage pulses, (2) a difference of width of said program voltage pulses, (3) a minimum voltage of said program voltage pulses and (4) a difference of voltage of said program voltage pulses.

10. A nonvolatile memory device according to claim 9,

wherein said setting circuit comprises a plurality of fuse circuits, and

wherein said trimming information is stored by said fuse circuits.

11. A semiconductor device on a semiconductor substrate, comprising:

a memory array including nonvolatile memory cells;

nonvolatile elements;

a programming circuit which is coupled to the nonvolatile elements and which performs a programming operation on selected ones of the nonvolatile memory cells by providing programming voltage pulses in accordance with an output of the nonvolatile elements.

12. A semiconductor device according to claim 11, wherein the nonvolatile elements have stored therein information for trimming a parameter of the programming voltage pulses.

13. A semiconductor device according to claim 12, wherein the parameter includes a minimum pulse width in the programming voltage pulses.

14. A semiconductor device according to claim 12, wherein the parameter includes a minimum voltage value in the programming voltage pulses.

15. A semiconductor device according to claim 12, wherein the parameter includes a pulse width difference on the programming voltage pulses.

16. A semiconductor device according to claim 12, wherein the parameter includes a voltage difference on the programming voltage pulses.

17. A semiconductor device according to claim 11, wherein the nonvolatile elements includes fuse elements.