Method and apparatus to support multi standard, multi service base-stations for wireless voice and data networks

• US 20020024993A1
• Filed: 12/29/2000
• Published: 02/28/2002
• Est. Priority Date: 12/30/1999
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Infineon Technologies AG
• Inventors: Subramanian, Ravi, Medlock, Joel D., Rieken, Keith, Woodthorpe, Christopher C., Jha, Uma
• Granted Patent: US 6,967,999 B2
• Time in Patent Office: Days
• US Class Current: 375/216
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0007 wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04W 24/00 Supervisory, monitoring or testing arrangements
• CPC Class Codes: H04W 28/10 Flow control between communication endpoints
• CPC Class Codes: H04W 88/08 Access point devices
• CPC Class Codes: H04W 88/10 adapted for operation in multiple networks, e.g. multi-mode access points

Abstract

An apparatus for digitally processing signals within wireless communications basestations which includes a channel pooling signal processor and a digital signal processor. The channel pooling signal processor includes a plurality of computation units typically realized in a heterogeneous multiprocessing architecture, a test interface for testing the function of the plurality of the computation units, a general-purpose microprocessor for managing the dataflow into and out of the channel pooling signal processor as well as effecting the control and configuration of the computation units, and an interconnect mechanism for connecting the plurality of computation units to the input, output, test interface, and the general-purpose microprocessor.

Claims

1. A signal processing apparatus, comprising:

a channel pooling signal processor, including;

a plurality of computation units;

a test interface for testing the function of said plurality of computation units;

a general purpose microprocessor for managing data flow into and out of said channel pooling signal processor; and

an interconnect mechanism for connecting said plurality of computation units, said test interface, and said general purpose microprocessor; and

a digital signal processor connected to said channel pooling signal processor;

wherein said channel pooling signal processor performs more computationally intensive signal processing operations and said digital signal processor performs less computationally intensive signal processing operations.

2. The signal processing apparatus of claim 1, wherein a computation unit of said plurality of computation units comprises:

a data sequencer for controlling program execution;

a configurable logic unit; and

a dedicated memory.

3. The signal processing apparatus of claim 1, further comprising:

a second channel pooling signal processor for processing multiple data streams of voice and data information.

4. The signal processing apparatus of claim 1, wherein said plurality of computation units are heterogenous computation units.

5. The signal processing apparatus of claim 1, wherein said plurality of computation units are homogeneous computation units.

6. A method for signal processing, comprising the steps of:

processing high complexity algorithms in a channel pooling signal processor, said channel pooling signal processor including;

a plurality of computation units;

a test interface for testing the function of said plurality of computation units;

a general purpose microprocessor for managing data flow into and out of said channel pooling signal processor; and

an interconnect mechanism for connecting said plurality of computation units, said test interface, and said general purpose microprocessor; and

processing low complexity algorithms in a digital signal processor connected to said channel pooling signal processor.

7. The method of claim 6, further comprising the steps of:

controlling program execution in a computation unit of said plurality of computation units;

configuring a configurable logic unit in said computation unit in accordance with a standard; and

storing program execution instructions in a dedicated memory in said computation unit.

8. The method of claim 6, further comprising the steps of:

processing multiple data streams of voice and data information in a second channel pooling signal processor.