Method for using thin spacers and oxidation in gate oxides

• US 20020025643A1
• Filed: 04/25/2001
• Published: 02/28/2002
• Est. Priority Date: 08/23/2000
• Status: Active Grant

• Current Assignee: Mohamed A. Ditali, Salman Akram
• Original Assignee: Mohamed A. Ditali, Salman Akram
• Inventors: Akram, Salman, Ditali, Mohamed A.
• Granted Patent: US 6,448,143 B1
• Time in Patent Office: Days
• US Class Current: 438/305
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A method for forming a lightly doped drain (LDD) field effect transistor uses very thin first sidewall spacers over the gate sidewalls, in which annealing/oxidation of the sidewall spacers results in (a) the rounding of corner portions of the gate structure sidewalls adjacent the gate oxide, and (b) a very low thermal consumption comprising a small portion of the total thermal budget. Secondary sidewall spacers of greater width are then formed to act as offsets in the introduction of N-type dopants into the substrate to form source and drain contact regions. The method may be varied to accommodate various design configurations and size scaling.

Claims

1. A method of forming a transistor on a substrate, comprising:

forming a dielectric layer on a substrate;

forming a gate structure on the dielectric layer having a gate oxide layer formed on said dielectric layer and having a metal silicide layer formed on said gate oxide layer, said gate structure having a first sidewall and a second sidewall for defining therebetween within said substrate a first contact region, a channel region and a second contact region;

forming first and second subregions within the second contact region, each subregion having a dopant concentration that differs from that of the other subregion, said forming of each said first and second subregions comprising;

depositing a thin conformal layer of dielectric material over said wafer;

anisotropically etching said layer of dielectric material for forming a first single thin layer sidewall spacer of dielectric material on said first sidewall and said second sidewall;

performing an annealing/oxidation process on the dielectric material on said first sidewall and said second sidewall;

forming a second single layer sidewall spacer overlying said first spacer, said second sidewall spacer; and

introducing a first dopant into the substrate to form said first subregion, said first subregion being generally aligned with said second sidewall spacer.

2. The method of claim 1, wherein the first sidewall spacer comprises an anisotropically etched layer of material having a thickness in the range of between about 50 and 150 Angstroms.

3. The method of claim 1, wherein the second sidewall spacer comprises a layer of material having a thickness of in the range of about 2 to 20 times the thickness of said first sidewall spacer.

4. The method of claim 1, wherein the second sidewall spacer comprises a layer of material having a thickness of about 550 Angstroms.

5. The method of claim 1, wherein said first sidewall spacer is formed of one of silicon nitride and silicon dioxide.

6. A method of forming a transistor on a substrate, comprising:

forming a dielectric layer on a substrate;

forming a gate structure on a portion of the dielectric layer having at least a gate oxide layer formed on said dielectric layer and a metal silicide layer formed on said gate oxide layer, said gate structure having a first sidewall and a second sidewall for defining therebetween within the substrate a first contact region, a channel region and a second contact region;

forming first and second subregions within the second contact region, each subregion having a dopant concentration that differs from that of the other subregion, said forming each said first and second subregions comprising;

depositing a first conformal layer of dielectric material over said wafer;

etching said first layer of dielectric material for forming a first layer sidewall spacer of dielectric material on said first sidewall and said second sidewall;

performing an annealing/oxidation process on the dielectric material on said first sidewall and said second sidewall;

depositing a second conformal layer of dielectric material for forming a second layer sidewall spacer of dielectric material on at least portions of said first sidewall and said second sidewall;

etching said second layer of dielectric material for forming a second layer sidewall spacer of dielectric material on said first sidewall and said second sidewall;

performing an annealing/oxidation process on the second layer of dielectric material on said first sidewall and said second sidewall; and

introducing a first dopant into the substrate to form said first subregion, said first subregion being generally aligned with said second sidewall spacer.

7. The method of claim 6, wherein said first sidewall spacer and said second sidewall spacer comprises one of silicon nitride and silicon dioxide.