Processor capable of enabling/disabling memory access

• US 20020026567A1
• Filed: 02/26/2001
• Published: 02/28/2002
• Est. Priority Date: 08/25/2000
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Fujitsu Limited
• Inventors: Mizoguchi, Kazuaki, Naito, Mutsuhiro
• Granted Patent: US 6,647,475 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 12/1441 for a range

Abstract

A low-end microprocessor 10 includes a stack pointer 18 storing a word SPV, a comparator 17 comparing the SPV with a given value ADR1, an inverter 19 inverting the compared result CP, and an AND gate 16 receiving a write request signal WR from a CPU 11 and the output of the inverter 19. The AND gate 16 provides its output to the write enable signal input WE of a memory 12 in order to determine enabling/disabling of writing according to the depth of stack.

Claims

1. A processor comprising:

(a) a stack pointer; and

(b) an access enable/disable determining circuit, comparing the contents of said stack pointer with a given value to provide a signal enabling/disabling memory access according to the comparison result.

2. The processor of claim 1, wherein said access enable/disable determining circuit provides said signal enabling/disabling memory access according to said comparison result when an address value falls in a given range.

3. The processor of claim 1, wherein said access enable/disable determining circuit includes:

(i) a comparator comparing the contents of said stack pointer with said given value; and

(ii) a logic circuit providing a signal enabling/disabling writing into a memory as said signal by making a write request signal effective/ineffective according to the comparison result of said comparator.

4. The processor of claim 1, wherein said access enable/disable determining circuit includes:

(i) a comparator comparing the contents of said stack pointer with said given value; and

(ii) a logic circuit providing a signal enabling/disabling reading from a memory as said signal by making a read request signal effective/ineffective according to the comparison result of said comparator.

5. The processor of claim 1, further comprising:

(c) a memory having a write enable input to receive said signal enabling/disabling memory access.

6. The processor of claim 2, further comprising:

(c) a memory having a write enable input to receive said signal enabling/disabling memory access.

7. The processor of claim 3, further comprising:

(c) a memory having a write enable input to receive said signal enabling/disabling memory access.

8. The processor of claim 4, further comprising:

(c) a memory having a write enable input to receive said signal enabling/disabling memory access.

9. The processor of claim 7, wherein said logic circuit receives said comparison result and said write request signal, provides said signal enabling/disabling writing, and sets said signal enabling/disabling writing at an enabling state when said write request signal is active, and said comparison result indicates that the contents of said stack pointer is larger than said given value.

10. The processor of claim 9, further comprising:

an address range determining circuit for providing an address range determining signal according to whether a present address falls in a given range,

wherein said logic circuit further receives said address range determining signal, and sets at said enabling state when said write request signal is active, said address range determining signal indicates that said present address falls in said given range, and said comparison result indicates that the contents of said stack pointer is larger than said given value.

11. The processor of claim 10, further comprising:

a CPU having an output to provide said write request signal.

12. The processor of claim 11, wherein said CPU has an interruption request input, and said processor further comprises another logic circuit for activating said interruption request input when said signal enabling/disabling writing is in said enabling state and said write request signal is active.

13. The processor of claim 12, further comprising:

a register for setting said given value.