ONE-TIME PROGRAMMABLE MEMORY CELL IN CMOS TECHNOLOGY
First Claim
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1. An OTP memory cell in CMOS technology, comprising a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region deeper and less doped than the source.
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Abstract
An OTP memory cell in CMOS technology, including a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region deeper and less doped than the source.
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Citations
21 Claims
- 1. An OTP memory cell in CMOS technology, comprising a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region deeper and less doped than the source.
- 8. A method for manufacturing an OTP anti-fuse memory cell in CMOS technology, comprising forming the drain regions of the unbalanced programming transistors of a first channel type simultaneously with the wells aimed at receiving MOS transistors of a second channel type.
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10. An array of non-volatile integrated memory cells, comprising:
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a plurality of capacitors formed within oxide layers; and
a plurality of write transistors, each write transistor coupled in series to a respective one of the capacitors to form a single memory cell coupled between a voltage source and a ground potential, the write transistor having a gate coupled to a control terminal of the wherein the write transistor is cut off during a read operation and is enabled during a write operation. - View Dependent Claims (11, 12, 14, 15, 17, 18, 19, 20, 21)
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13. A non-volatile integrated memory cell architecture, comprising:
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first and second capacitors having an oxide formed at transistor gate level, each capacitor having a first terminal coupled to a voltage source and a second terminal;
first and second transistors, each transistor having a drain terminal coupled to the second terminal of a respective one of the first and second capacitors to form first and second nodes, respectively, and each transistor further having a source terminal coupled to a ground potential and a gate terminal coupled to first and second select lines, respectively;
a read circuit having first and second inputs and having first and second complementary outputs; and
first and second switches having first terminals coupled to the first and second nodes, respectively, and second terminals coupled to the first and second inputs of the read circuit, respectively, and each switch having a control terminal coupled to a common control line.
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16. A method of forming an OTP non-volatile memory cell with CMOS technology, comprising:
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forming an unbalanced transistor, the drain of the transistor formed in a well of same conductivity type as a channel of the transistor; and
forming a capacitor associated in series with the unbalanced programming transistor.
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Specification