ONE-TIME PROGRAMMABLE MEMORY CELL IN CMOS TECHNOLOGY

• US 20020027822A1
• Filed: 12/22/1999
• Published: 03/07/2002
• Est. Priority Date: 12/23/1998
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Schoellkopf, Jean-Pierre, Candelier, Philippe
• Granted Patent: US 6,421,293 B1
• Time in Patent Office: Days
• US Class Current: 365/225.7
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

An OTP memory cell in CMOS technology, including a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region deeper and less doped than the source.

Claims

1. An OTP memory cell in CMOS technology, comprising a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region deeper and less doped than the source.

2. The cell of claim 1 wherein this series association is connected between two terminals of application of a supply voltage.

3. The cell of claim 1 wherein a first electrode of the capacitor is formed by said region.

4. The cell of claim 1 wherein the capacitor is formed in an oxide level constitutive of the transistor gate.

5. The cell of claim 4 wherein a second electrode of the capacitor is adapted to receive in read mode a relatively low voltage, and in programming mode a relatively high voltage.

6. The cell of claim 5 wherein the transistor and the capacitor are sized so that, in a programming cycle and for an unselected cell, the voltage across the capacitor remains smaller than its breakdown voltage when the currents in the capacitor and in the transistor are balanced.

7. The cell of claim 6 wherein the transistor is sized to limit the current in a selected cell while allowing a breakdown of the oxide constitutive of the capacitor.

8. A method for manufacturing an OTP anti-fuse memory cell in CMOS technology, comprising forming the drain regions of the unbalanced programming transistors of a first channel type simultaneously with the wells aimed at receiving MOS transistors of a second channel type.

9. The method of claim 8, wherein a capacitor serially connected with each unbalanced programming transistor has a first electrode made of the drain region of said transistor.

10. An array of non-volatile integrated memory cells, comprising:

a plurality of capacitors formed within oxide layers; and

a plurality of write transistors, each write transistor coupled in series to a respective one of the capacitors to form a single memory cell coupled between a voltage source and a ground potential, the write transistor having a gate coupled to a control terminal of the wherein the write transistor is cut off during a read operation and is enabled during a write operation.

11. The memory cell of claim 10 wherein each write transistor is unbalanced with a drain formed in a well having the same conductivity type as the write transistor channel, and wherein each capacitor has an oxide level that is the level of gate oxide for the write transistors, each capacitor further having a first electrode formed in the well as the write transistor drain and a second electrode configured to accept a first voltage in a read mode and a second voltage in a write mode, the second voltage having a voltage level higher than the first voltage and great enough to break down the oxide of the capacitor.

12. The memory cell of claim 11 wherein each write transistor is sized to limit current in the associated memory cell while enabling breakdown of the capacitor oxide, and wherein each write transistor and capacitor are sized to limit voltage across the capacitor to less than the capacitor'"'"'s breakdown voltage when the capacitor is unselected during a write operation.

14. The memory cell architecture of claim 13 wherein each transistor is unbalanced with a drain formed in a well having the same conductivity type as the transistor channel, and wherein each capacitor has an oxide level that is the level of gate oxide for the transistors, each capacitor further having a first electrode formed in the well as the transistor drain and a second electrode configured to accept a first voltage in a read mode and a second voltage in a write mode, the second voltage having a voltage level higher than the first voltage and great enough to break down the oxide of the capacitor.

15. The memory cell architecture of claim 14 wherein each transistor is sized to limit current in the associated memory cell while enabling breakdown of the capacitor oxide, and wherein each transistor and capacitor are sized to limit voltage across the capacitor to less than the capacitor'"'"'s breakdown voltage when the capacitor is unselected during a write operation.

17. The method of claim 16 wherein the capacitor is formed to have a first electrode formed in the well in which the drain of the transistor is formed.

18. The method of claim 16 wherein the capacitor is formed in an oxide level that is constitutive of the transistor gate.

19. The method of claim 18 wherein the capacitor is formed to have a second electrode that is configured to accept a first voltage in a read mode and a second voltage in a write mode, the second voltage being higher than the first voltage and great enough to break down the oxide of the capacitor to enable writing of data to the capacitor.

20. The method of claim 18 wherein the transistor and the capacitor are formed to a size that the voltage across the capacitor remains smaller than its breakdown voltage when the current in the capacitor and in the transistor are balanced during a write operation when the capacitor is unselected for writing data.

21. The method of claim 20 wherein the transistor is formed to a size that limits current in the memory cell while allowing a breakdown of the capacitor oxide.

13. A non-volatile integrated memory cell architecture, comprising:

first and second capacitors having an oxide formed at transistor gate level, each capacitor having a first terminal coupled to a voltage source and a second terminal;

first and second transistors, each transistor having a drain terminal coupled to the second terminal of a respective one of the first and second capacitors to form first and second nodes, respectively, and each transistor further having a source terminal coupled to a ground potential and a gate terminal coupled to first and second select lines, respectively;

a read circuit having first and second inputs and having first and second complementary outputs; and

first and second switches having first terminals coupled to the first and second nodes, respectively, and second terminals coupled to the first and second inputs of the read circuit, respectively, and each switch having a control terminal coupled to a common control line.

16. A method of forming an OTP non-volatile memory cell with CMOS technology, comprising:

forming an unbalanced transistor, the drain of the transistor formed in a well of same conductivity type as a channel of the transistor; and

forming a capacitor associated in series with the unbalanced programming transistor.