Method of controlling data sampling clocking of asynchronous network nodes in a frame-based communications network

• US 20020027886A1
• Filed: 04/04/2001
• Published: 03/07/2002
• Est. Priority Date: 04/07/2000
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Fischer, Matthew James, Mallory, Tracy D.
• Granted Patent: US 6,975,655 B2
• Time in Patent Office: Days
• US Class Current: 370/255
• CPC Class Codes: H04L 1/0003 by switching between different modulation schemes
• CPC Class Codes: H04L 1/0005 applied to payload information
• CPC Class Codes: H04L 1/0006 by adapting the transmission format
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0025 Transmission of mode-switching indication
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 1/08 by repeating transmission, e.g. Verdan system H04L1/1858 and H04L1/189 take precedence
• CPC Class Codes: H04L 1/18 Automatic repetition systems, e.g. Van Duuren systems
• CPC Class Codes: H04L 1/1809 Selective-repeat protocols
• CPC Class Codes: H04L 1/1848 Time-out mechanisms
• CPC Class Codes: H04L 1/1877 for semi-reliable protocols, e.g. for less sensitive applications like streaming video buffer level management for video bitstream control arrangements H04N21/44004
• CPC Class Codes: H04L 1/1883 using multiple timers
• CPC Class Codes: H04L 1/1887 Scheduling and prioritising arrangements
• CPC Class Codes: H04L 1/20 using signal quality detector
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/4013 Management of data rate on the bus systems modifying transmission characteristics according to link quality H04L1/0001
• CPC Class Codes: H04L 12/40136 Nodes adapting their rate to the physical link properties LAN switches H04L49/351
• CPC Class Codes: H04L 12/40156 by using dedicated slots associated with a priority level
• CPC Class Codes: H04L 12/40163 by assigning priority to messages according to a message field
• CPC Class Codes: H04L 12/403 : with centralised control, e.g. polling
• CPC Class Codes: H04L 12/4035 : in which slots of a TDMA packet structure are assigned based on a contention resolution carried out at a master unit TDM/TDMA multiplex systems per se H04J3/1694; hybrid switching systems H04L12/64
• CPC Class Codes: H04L 12/407 : with decentralised control
• CPC Class Codes: H04L 12/413 : with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 12/417 : with deterministic access, e.g. token passing
• CPC Class Codes: H04L 2001/0093 : Point-to-multipoint
• CPC Class Codes: H04L 2001/125 : Arrangements for preventing errors in the return channel
• CPC Class Codes: H04M 11/00 : Telephonic communication systems specially adapted for combination with other electrical systems
• CPC Class Codes: H04M 11/06 : Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method of controlling data sampling clocking of asynchronous network nodes, each asynchronous network node having a local clock and transmitting and receiving packets to and from an asynchronous network according to an asynchronous network media access protocol. An asynchronous network node capable of transmitting and receiving packets on the asynchronous network is designated as a master node. Each non-master asynchronous network node which desires to synchronously transport packets across the asynchronous network is designated as a slave node. A master node clock of the master node is synchronized with a slave node clock of each slave node. Each slave node clock is continuously corrected compared with the master node clock to smooth slave clock error to an average of zero compared with the master clock as a reference using timestamp information from the master node. A derivative clock at the slave node is derived from the continuously correcting each slave node clock to control data sampling at the slave node.

Claims

1. A method of controlling data sampling clocking of asynchronous network nodes, each asynchronous network node having a local clock and transmitting and receiving packets to and from an asynchronous network according to an asynchronous network media access protocol, comprising:

designating as a master node an asynchronous network node capable of transmitting and receiving packets on the asynchronous network;

designating as a slave node each non-master asynchronous network node which desires to synchronously transport packets across the asynchronous network;

synchronizing a master node clock of the master node with a slave node clock of each slave node;

continuously correcting each slave node clock compared with the master node clock to smooth slave clock error to an average of zero compared with the master clock as a reference using timestamp information from the master node; and

deriving a derivative clock at the slave node from the continuously correcting each slave node clock to control data sampling at the slave node.

2. The method of claim 1, wherein the step of designating a master node is determined by assessing an ability of an asynchronous node to directly access synchronous network timing information.

3. The method of claim 2, wherein an asynchronous network node with direct access to synchronous network timing information is designated the master node.

4. The method of claim 1, wherein synchronizing further includes:

sending timestamp report messages in pairs from the master node to slave nodes at periodic intervals by;

sending a first timestamp report message from the master node to the slave nodes;

recording master timestamp information at the master node at a defined time during transmission of the first timestamp report message of a pair corresponding to the transmission of the first timestamp report message of a pair; and

sending a second timestamp report message from the master node to the slave nodes which contains the master timestamp information; and

receiving timestamp report messages in pairs by the slave nodes from the master node by;

recording a slave timestamp at the slave nodes at a fixed time during reception of each timestamp report message to provide a recorded timestamp of the first timestamp report message at the slave nodes;

comparing the recorded timestamp of the first timestamp report message of each pair at the particular slave node with the master timestamp information from within the second timestamp report message of the same pair to determine a master clock offset from the slave clock of the slave nodes; and

adjusting the slave clock of the slave nodes to be synchronized with the master clock based on the master clock offset.

5. The method of claim 1, wherein continuously correcting includes:

using a continuing series of calculated master clock offsets from the slave clock to calculate a correction factor for the slave clock, the additional calculated master clock offsets being determined from additional received timestamp report message pairs following the synchronization step; and

tracking error of the slave clock as compared with the master clock and modifying slave clock frequency to smooth the error and create a continuously corrected slave clock with an average error of zero as compared to the master clock.

6. The method of claim 1, wherein the step of deriving a derivative clock includes selecting a pair of integers to be used to divide in serial stages a synchronized tracked slave clock to a lower frequency to control the data sampling clocking.