Mosfet with high dielectric constant gate insulator and minimum overlap capacitance

• US 20020028555A1
• Filed: 05/25/2001
• Published: 03/07/2002
• Est. Priority Date: 02/14/2000
• Status: Active Grant

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Hanafi, Hussein Ibrahim, Natzle, Wesley Charles, Boyd, Diane Catherine, Ieong, Meikei
• Granted Patent: US 6,353,249 B1
• Time in Patent Office: Days
• US Class Current: 438/299
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/μm or below) and a channel length (sub-lithographic, e.g., 0.1 μm or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.

Claims

1. A method of forming a MOSFET device having low overlap capacitance and a short channel length comprising the steps of:

(a) providing a semiconductor structure having a film stack formed on a surface of a substrate, said film stack comprising at least a pad oxide layer formed on said surface of said substrate and a nitride layer formed on said pad oxide layer;

(b) forming a gate hole in said nitride layer stopping on said pad oxide layer;

(c) forming an oxide layer on said nitride layer in said gate hole;

(d) etching said oxide layer and a portion of said pad oxide layer so as to provide an opening in said gate hole exposing said substrate, wherein the pad oxide layer is tapered by said etching;

(e) forming a high-k, high-temperature metal oxide layer about said gate hole and on said exposed substrate;

(f) filling said gate hole with gate conductor;

(g) removing said nitride layer exposing portions of said high k, high-temperature metal oxide; and

(h) completing fabrication of said MOSFET device.

2. The method of claim 1 wherein step (h) includes forming activated source/drain extensions in said substrate beneath said gate conductor;

forming spacers on said exposed high-k, high-temperature metal oxide;

forming activated source/drain regions in said substrate; and

forming silicide regions in portions of said pad oxide and in said gate conductor.

3. The method of claim 1 wherein said substrate includes isolation regions formed therein.

4. The method of claim 3 wherein said isolation regions include an oxide liner and a trench dielectric material.

5. The method of claim 1 wherein said substrate is a semiconducting material selected from the group consisting of Si, Ge, SiGe, GaAs, InAs, InP and layered semiconductors.

6. The method of claim 1 wherein said gate hole is formed by lithography and etching.

7. The method of claim 1 wherein said oxide layer is formed by deposition of an oxide material.

8. The method of claim 1 wherein step (d) is conducted utilizing a chemical oxide removal process.

9. The method of claim 8 wherein said chemical oxide removal process is conducted in a vapor of HF and NH₃.

10. The method of claim 8 wherein said chemical oxide removal process is carried out at a pressure of about 8 millitorr or below.

11. The method of claim 1 wherein said high-k, high-temperature metal oxide is Al₂O₃ or TiO₂ or any other oxide that is capable of withstanding degradation using a 950°

-1050°

C., 10 second anneal.

12. The method of claim 1 wherein said high-k, high-temperature metal oxide is formed by a deposition process selected from the group consisting of chemical vapor deposition (CVD), plasma-assisted CVD, sputtering, atomic layer deposition and other like deposition processes.

13. The method of claim 1 wherein said high-k, high-temperature metal oxide has a thickness of from about 5 to about 30 Å

.

14. The method of claim 1 wherein said gate conductor is polysilicon, W, Ta, TiN and other like conductors.

15. The method of claim 1 wherein step (g) comprises a damascene processing step, wherein a chemical etchant is employed.

17. The method of claim 16 wherein said substrate includes isolation regions formed therein.

18. The method of claim 17 wherein said isolation regions include an oxide liner and a trench dielectric material.

19. The method of claim 16 wherein said substrate is a semiconducting material selected from the group consisting of Si, Ge, SiGe, GaAs, InAs, InP and layered semiconductors.

20. The method of claim 16 wherein step (i) comprises providing a resist, patterning said resist and etching areas not including the patterned resist.

21. The method of claim 16 wherein said SiO₂ layer is removed utilizing a chemical etchant.

22. The method of claim 16 wherein said insulator layer is formed by a deposition process selected from the group consisting of CVD, low pressure CVD, plasma-assisted CVD and other like deposition processes that are capable of forming a conformal layer.

23. The method of claim 16 wherein said planarizing is carried out by chemical-mechanical polishing or grinding.

24. The method of claim 16 wherein step (x) is conducted utilizing a chemical oxide removal process.

25. The method of claim 24 wherein said chemical oxide removal process is conducted in a vapor of HF and NH₃.

26. The method of claim 24 wherein said chemical oxide removal process is carried out at a pressure of about 8 millitorr or below.

27. The method of claim 1 wherein said high-k, low-temperature metal oxide is ZrO₂, barium titanate, strontium titanate and barium strontium titanate, or any other oxide that degrades when a 950°

-1050°

C., 10 second anneal is employed.

28. The method of claim 16 wherein said high-k, low-temperature metal oxide is formed by a deposition process selected from the group consisting of chemical vapor deposition (CVD), plasma-assisted CVD, sputtering, atomic layer deposition and other like deposition processes.

29. The method of claim 16 wherein said high-k, low-temperature metal oxide has a thickness of from about 5 to about 30 Å

.

30. The method of claim 16 wherein said high-k, low-temperature oxide is annealed in N₂ at a temperature of about 950°

C. or below and for a time period of from about 30 seconds or less.

31. The method of claim 16 wherein said gate conductor is polysilicon, W, Ta, TiN and other like conductors.

16. A method of forming a MOSFET device having low overlap capacitance and a short channel length comprising the steps of:

(i) providing a semiconductor structure having a dummy film stack formed on a surface of a substrate, said dummy film stack comprising at least a pad oxide layer formed on said surface of said substrate, a polysilicon layer on said pad oxide layer, and a SiO₂ layer formed on said polysilicon layer;

(ii) removing selective portions of said dummy film stack stopping on said pad oxide layer so as to provide a patterned dummy gate region;

(iii) removing said SiO₂ layer from said patterned dummy gate region;

(iv) forming activated source/drain extensions in said substrate beneath said dummy gate region;

(v) forming spacers on sidewalls of said dummy gate region;

(vi) forming activated source/drain regions in said substrate;

(vii) forming silicide regions in portions of said pad oxide layer and in said polysilicon layer of said dummy gate region;

(viii) forming an insulator layer surrounding said dummy gate region;

(ix) planarizing said insulator layer stopping at said polysilicon layer in said dummy gate region;

(x) forming an opening so as to expose a portion of said substrate, said opening being formed by removing said polysilicon layer of said dummy gate and by tapering a portion of said pad oxide layer of said dummy gate;

(xi) forming a high-k, low-temperature metal oxide in said opening; and

(xii) filling said opening with a gate conductor deposited at low temperatures

32. A MOSFET device comprising at least one gate region formed on a semiconductor substrate, said gate region comprising a gate conductor, a gate insulator and spacers, said gate insulator is a high-k metal oxide having a dielectric constant of greater than 7.0, said gate region further comprising a sub-lithographic channel formed beneath said gate insulator, wherein said channel length is determined by forming a portion of said gate insulator on a tapered pad oxide layer.