Damage-free sculptured coating deposition

• US 20020029958A1
• Filed: 06/20/2001
• Published: 03/14/2002
• Est. Priority Date: 11/26/1997
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Chiang, Tony, Ding, Peijun, Chin, Barry L., Zhang, Hong, Xu, Zheng, Chen, Fusen E., Yao, Gongda, Kohara, Gene Y.
• Granted Patent: US 6,758,947 B2
• Time in Patent Office: Days
• US Class Current: 204/192.1
• CPC Class Codes: C23C 14/046 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 14/165 by cathodic sputtering
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76862 Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material

Abstract

We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

Claims

1. A method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of:

a) applying a first portion of a sculptured layer using traditional sputtering or ion deposition sputtering in combination with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor feature performance or longevity; and

b) applying a subsequent portion of said sculptured layer using ion deposition sputtering with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material.

2. The method of claim 1, wherein said sculptured layer exhibits a substantially uniform thickness.

3. The method of claim 1 or claim 2, wherein said sculptured layer is a barrier layer or a wetting layer.

4. The method of claim 3, wherein the minimum thickness of said barrier layer or setting layer at any point on said semiconductor feature surface is about 5 Å

.

5. The method of claim 4, wherein said semiconductor feature size is less than about 5 μ

m with an aspect ratio of at least 1.

6. The method of claim 5, wherein said semiconductor feature size is less than about 0.5 μ

m with an aspect ratio of at least 3.

7. The method of claim 3, wherein said barrier layer comprises a material selected from the group consisting of Ta, TaN, TaSiN, Mo, MoN, MoSiN, TiN, TiSiN, W, WN, WSiN, and combinations thereof.

8. The method of claim 3, wherein said wetting layer comprises a material selected from the group consisting of Ta, Mo, Ti, and combinations thereof.

9. The method of claim 3, wherein said barrier layer is selected form the group consisting of Ti, TiN, and combinations thereof.

10. The method of claim 1 or claim 2, wherein said sculptured layer is a seed layer of a conductive material.

11. The method of claim 10, wherein said conductive material is selected from the group consisting of Cu, Al, Ag, Ni, Au, W, and Pt.

12. The method of claim 11, wherein said conductive material is copper.

13. The method of claim 7, minimum thickness of said seed layer at any point on said semiconductor feature surface is about 5 Å

.

14. The method of claim 13, wherein said semiconductor feature size is less than about 5 μ

m with an aspect ratio of at least 1.

15. The method of claim 14, wherein said semiconductor feature size is less than about 0.5 μ

m with an aspect ratio of at least 3.

16. The method of claim 1 or claim 2, wherein said substrate bias applied during the deposition of said first portion of said sculptured layer is less than about −

20 V.

17. The method of claim 1 or claim 2, wherein no substrate bias is applied during the deposition of said first portion of said sculptured layer.

18. The method of claim 1, or claim 2, wherein said substrate bias applied during said subsequent portion of said sculptured layer is greater than about −

20 V.

19. The method of claim 17, wherein said substrate bias applied during said subsequent portion of said sculptured layer is greater than about −

20 V.

20. The method of claim 18, wherein said first portion of said sculptured layer is deposited using an IMP technique at a process chamber pressure of at least about 1 mT.

21. The method of claim 19, wherein said first portion of said sculptured layer is deposited using an IMP technique at a process chamber pressure of at least about 1 mT.

22. The method of claim 20, wherein said first portion of said sculptured layer is deposited using an IMP technique at a process chamber pressure of at least about 10 mT.

23. The method of claim 21, wherein said first portion of said sculptured layer is deposited using an IMP technique at a process chamber pressure of at least about 10 mT.

24. The method of claim 18, wherein said first portion of said sculptured layer is deposited using a standard sputtering technique at a process chamber pressure of 10 mT or less.

25. The method of claim 18, wherein said second portion of said sculptured layer is deposited using an IMP technique at a process chamber pressure of at least about 1 mT.

26. The method of claim 19, wherein said second portion of said sculptured layer is deposited using an IMP technique at a process chamber pressure of at least about 1 mT.

27. The method of claim 20, wherein said second portion of said sculptured layer is deposited using an IMP technique at a process chamber pressure of at least about 10 mT.

28. The method of claim 21, wherein said first portion of said sculptured layer is deposited using an IMP technique at a process chamber pressure of at least about 10 mT.

29. The method of claim 12, wherein said substrate temperature during application of said copper seed layer is less than about 500°

C.

30. The method of claim 29, wherein said substrate temperature is less than about 200°

C.