Methods for fabricating light emitting devices having aluminum gallium indium nitride structures and mirror stacks

• US 20020030198A1
• Filed: 08/06/2001
• Published: 03/14/2002
• Est. Priority Date: 02/05/1999
• Status: Active Grant

• Current Assignee: Arto V. Nurmikko, Carrie Carter-Coman, Fred A. Kish, Michael R. Krames, R. Scott Kern, Yoon-Kyu Song
• Original Assignee: Arto V. Nurmikko, Carrie Carter-Coman, Fred A. Kish, Michael R. Krames, R. Scott Kern, Yoon-Kyu Song
• Inventors: Song, Yoon-Kyu, Krames, Michael R., Kish, Fred A. Jr., Nurmikko, Arto V., Kern, R. Scott, Coman, Carrie Carter
• Granted Patent: US 6,420,199 B1
• Time in Patent Office: Days
• US Class Current: 257/103
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/105 with a resonant cavity structure
• CPC Class Codes: H01L 33/465 with a resonant cavity structure
• CPC Class Codes: H01S 5/0216 using an intermediate compound, e.g. a glue or solder
• CPC Class Codes: H01S 5/0217 Removal of the substrate
• CPC Class Codes: H01S 5/18341 Intra-cavity contacts
• CPC Class Codes: H01S 5/18361 Structure of the reflectors, e.g. hybrid mirrors
• CPC Class Codes: H01S 5/1838 Reflector bonded by wafer fusion or by an intermediate compound
• CPC Class Codes: H01S 5/34333 with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.

Claims

1. A device comprising:

a substrate;

an Al_xGa_yIn_zN structure including a n-type layer, a p-type layer, and an active layer, positioned proximate to the substrate;

a first mirror stack, interposing the substrate and a bottom side of the Al_xGa_yIn_zN structure;

a wafer bonded interface, interposing the first mirror stack and a selected one of the substrate and Al_xGa_yIn_zN structure, having a bonding temperature; and

a p and an n contact, the p contact electrically connected to the p-type layer, the n contact electrically connected to the n-type layer.

2. A device, as defined in claim 1, further comprising:

at least one intermediate bonding layer, adjacent the wafer bonded interface; and

one of the intermediate bonding layer and the substrate is selected to be compliant.

3. A device, as defined in claim 2, wherein the Al_xGa_yIn_zN device is a vertical cavity optoelectronic structure.

4. A device, as defined in claim 3, wherein the Al_xGa_yIn_zN device further including a current constriction layer within the p-type layer.

5. A device, as defined in claim 2, wherein the substrate is compliant and is selected from a group that includes gallium phosphide (GaP), gallium arsenide (GaAs), indium phosphide (InP), and silicon (Si).

6. A device, as defined in claim 2, wherein the intermediate bonding layer is compliant and selected from a group that includes dielectrics and alloys containing halides, ZnO, indium, tin, chrome (Cr), gold, nickel, and copper, and II-VI materials.

7. A device, as defined in claim 2, further comprising a second mirror stack positioned adjacent a top side of the Al_xGa_yIn_zN structure.

8. A device, as defined in claim 7, wherein at least one of the first and second mirror stacks is selected from a group that includes dielectric distributed Bragg reflectors and composite distributed Bragg reflectors.

9. A device, as defined in claim 1, further comprising a second mirror stack positioned adjacent the Al_xGa_yIn_zN structure.

10. A device, as defined in claim 9, wherein at least one of the first and second mirror stacks is selected from a group that includes dielectric distributed Bragg reflectors and composite distributed Bragg reflectors.

11. A device, as defined in claim 1, wherein the Al_xGa_yIn_zN device further including a current constriction layer within the p-type layer.

12. A device, as defined in claim 1, wherein the substrate is compliant and is selected from a group that includes gallium phosphide (GaP), gallium arsenide (GaAs), indium phosphide (InP), and silicon (Si).

13. A device, as defined in claim 1, wherein the Al_xGa_yIn_zN device is a vertical cavity optoelectronic structure.

15. A method for fabricating an Al_xGa_yIn_zN structure, as defined in claim 14, wherein the step for removing the sacrificial growth substrate comprises the step of laser melting.

16. A method for fabricating an Al_xGa_yIn_zN structure, as defined in claim 14, further comprising the step of attaching an intermediate bonding layer at the wafer bond interface.

17. A method for fabricating an Al_xGa_yIn_zN structure, as defined in claim 16, wherein one of the host substrate and the intermediate bonding layer is selected to be compliant.

18. A method for fabricating a Al_xGa_yIn_zN structure, as defined in claim 14, further comprising the step of attaching a second mirror stack on top of the Al_xGa_yIn_zN structure.

20. A method for fabricating an Al_xGa_yIn_zN structure, as defined in claim 19, wherein the step for removing the sacrificial growth substrate comprises the step of laser melting.

21. A method for fabricating an Al_xGa_yIn_zN structure, as defined in claim 19, further comprising the step of attaching an intermediate bonding layer at the wafer bond interface.

22. A method for fabricating an Al_xGa_yIn_zN structure, as defined in claim 19, wherein one of the host substrate and the intermediate bonding layer is selected to be compliant.

23. A method for fabricating a Al_xGa_yIn_zN structure, as defined in claim 19, further comprising the step of attaching a second mirror stack on top of the Al_xGa_yIn_zN structure.

14. A method for fabricating a Al_xGa_yIn_zN structure, comprising the steps of:

attaching a host substrate to a first mirror stack;

fabricating a Al_xGa_yIn_zN structure on a sacrificial growth substrate;

creating a wafer bond interface;

removing the sacrificial growth substrate; and

depositing electrical contacts to the Al_xGa_yIn_zN structure.

19. A method for fabricating a Al_xGa_yIn_zN structure comprising the steps of:

fabricating a Al_xGa_yIn_zN structure to a sacrificial growth substrate;

attaching a first mirror stack on top of a Al_xGa_yIn_zN structure;

wafer bonding a host substrate to the first mirror stack to create a wafer bond interface;

removing the sacrificial growth substrate; and

depositing electrical contacts to the Al_xGa_yIn_zN structure.