Semiconductor device, method of fabricating the same, stack-type semiconductor device, circuit board and electronic instrument

• US 20020030245A1
• Filed: 06/01/2001
• Published: 03/14/2002
• Est. Priority Date: 06/02/2000
• Status: Active Grant

• Current Assignee: Advanced Interconnect Systems Limited (Vector Capital Corporation)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Wada, Kenji, Hanaoka, Terunao
• Granted Patent: US 6,720,661 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method of fabricating a semiconductor device including: a first step of forming a through hole in a semiconductor element having electrodes on a first surface; and a second step of forming a conductive layer which is electrically connected to the electrodes and is provided from the first surface through an inner wall of the through hole to a second surface of the semiconductor element which is opposite to the first surface. The conductive layer is formed to have connecting portions on the first and second surfaces so that a distance between at least two electrodes among the electrodes is different from a distance between the connecting portions on at least one of the first and second surfaces, in the second step.

Claims

1. A method of fabricating a semiconductor device comprising:

a first step of forming a through hole in a semiconductor element having a plurality of electrodes on a first surface; and

a second step of forming a conductive layer which is electrically connected to the electrodes and is provided from the first surface through an inner wall of the through hole to a second surface of the semiconductor element which is opposite to the first surface,

wherein the conductive layer is formed to have connecting portions on the first and second surfaces so that a distance between at least two electrodes among the plurality of electrodes is different from a distance between the connecting portions on at least one of the first and second surfaces, in the second step.

2. The method of fabricating a semiconductor device as defined in claim 1.

wherein a small hole which has a diameter smaller than a diameter of the through hole is previously formed and enlarged to form the through hole, in the first step.

3. The method of fabricating a semiconductor device as defined in claim 2,

wherein a depression is formed at a position in which the small hole is to be formed.

4. The method of fabricating a semiconductor device as defined in claim 2,

wherein the small hole is formed by a laser beam and the small hole is enlarged by wet etching.

5. The method of fabricating a semiconductor device as defined in claim 1,

wherein a hole communicating with the through hole is formed in each of the electrodes.

6. The method of fabricating a semiconductor device as defined in claim 1, wherein:

the through hole is formed in an end portion of the semiconductor element; and

the connecting portions are disposed in a center portion of the semiconductor element, on the inside of the through hole.

7. The method of fabricating a semiconductor device as defined in claim 1 further comprising,

a step of forming a stress relieving layer on at least one of the first and second surfaces before the second step,

wherein the conductive layer is formed to reach the stress relieving layer in the second step.

8. The method of fabricating a semiconductor device as defined in claim 7, wherein:

in the step of forming a stress relieving layer, the stress relieving layer comprises a plurality of projections; and

in the second step, the conductive layer is formed to reach the projections.

9. The method of fabricating a semiconductor device as defined in claim 7, wherein:

in the step of forming a stress relieving layer, the stress relieving layer comprises a plurality of projections,

a plurality of recessed portions are formed between the adjacent projections; and

in the second step, the conductive layer is formed to reach the recessed portions.

10. The method of fabricating a semiconductor device as defined in claim 7,

wherein the stress relieving layer is formed of a resin.

11. The method of fabricating a semiconductor device as defined in claim 7,

wherein the connecting portions are formed on the stress relieving layer.

12. The method of fabricating a semiconductor device as defined in claim 1,

wherein a distance between adjacent connecting portions among the connecting portions is wider than a distance between adjacent electrodes among the plurality of electrodes.

13. The method of fabricating a semiconductor device as defined in claim 1, further comprising

a step of providing external terminals at the connecting portions.

14. The method of fabricating a semiconductor device as defined in claim 13,

wherein in the step of providing the external terminals, a solder is provided into a thick layer on the connecting portions to form solder balls by wet back.

15. The method of fabricating a semiconductor device as defined in claim 13,

wherein a solder is provided on the connecting portions by electroplating or printing.

16. The method of fabricating a semiconductor device as defined in claim 1, further comprising

a step of forming a protective film over an area except at least the connecting portions after the second step.

17. The method of fabricating a semiconductor device as defined in claim 1, further comprising

a step of forming an insulating film over an area including the inner wall of the through hole after the first step and before the second step,

wherein the conductive layer is formed on the insulating film in the second step.

18. The method of fabricating a semiconductor device as defined in claim 17,

wherein the insulating film is formed by coating a resin over an area including the inner wall of the through hole.

19. The method of fabricating a semiconductor device as defined in claim 17, wherein:

the through hole is filled with a resin in the step of forming the insulating film; and

the conductive layer is formed within the through hole, through the resin in the second step.

20. The method of fabricating a semiconductor device as defined in claim 1.

wherein the semiconductor element is a semiconductor chip.

21. The method of fabricating a semiconductor device as defined in claim 1,

wherein the semiconductor element is a part of a semiconductor wafer.

22. The method of fabricating a semiconductor device, comprising,

a step of stacking semiconductor devices fabricated by the method as defined in claim 1, and electrically connecting adjacent two semiconductor devices by the conductive layer.

23. The method of fabricating a semiconductor device, comprising the steps of:

stacking semiconductor devices fabricated by the method as defined in claim 21, and electrically connecting adjacent two semiconductor devices by the conductive layer; and

cutting the semiconductor wafer into separate pieces.

25. The semiconductor device as defined in claim 24, wherein:

the through hole is formed in an end portion of the semiconductor element; and

the connecting portions are disposed in a center portion of the semiconductor element, on the inside of the through hole.

26. The semiconductor device as defined in claim 24, further comprising

a stress relieving layer formed on at least one of the first and second surfaces.

wherein the conductive layer is formed to reach the stress relieving layer.

27. The semiconductor device as defined in claim 26, wherein:

the stress relieving layer comprises a plurality of projections; and

the conductive layer is formed to reach the projections.

28. The semiconductor device as defined in claim 26, wherein;

the stress relieving layer comprises a plurality of projections;

a plurality of recessed portions are formed between the adjacent projections; and

the conductive layer is formed to reach the recessed portions.

29. The semiconductor device as defined in claim 26,

wherein the stress relieving layer is formed of a resin.

30. The semiconductor device as defined in claim 26,

wherein the connecting portions are formed on the stress relieving layer.

31. The semiconductor device as defined in claim 24,

wherein a distance between adjacent connecting portions among the connecting portions is wider than a distance between adjacent electrodes among the plurality of electrodes.

32. The semiconductor device as defined in claim 24, further comprising

external terminals provided at the connecting portions.

33. The semiconductor device as defined in claim 24,

wherein a protective film is formed over an area except the connecting portions.

34. The semiconductor device as defined in claim 24, wherein:

an insulating film is formed over an area including the inner wall of the through hole; and

the conductive layer is formed on the insulating film.

35. The semiconductor device as defined in claim 24,

wherein the semiconductor element is a semiconductor chip.

36. The semiconductor device as defined in claim 24,

wherein the semiconductor element is a part of a semiconductor wafer.

37. A stack-type semiconductor device formed by stacking a plurality of semiconductor devices.

wherein at least an undermost semiconductor device among the plurality of semiconductor devices is the semiconductor device as defined in claim 24.

38. A stack-type semiconductor device formed by stacking a plurality of the semiconductor devices as defined in claim 24,

wherein adjacent semiconductor devices among the plurality of the semiconductor devices are electrically connected by the conductive layer.

39. A stack-type semiconductor device formed by stacking a plurality of the semiconductor devices as defined in claim 27, wherein:

adjacent semiconductor devices among the plurality of the semiconductor devices are electrically connected by the conductive layer; and

in a pair of semiconductor devices among the plurality of the stacked semiconductor devices, the projections of the stress relieving layers are arranged to face each other.

40. A stack-type semiconductor device, comprising a first semiconductor device and a second semiconductor device which are stacked,

wherein the first semiconductor device is the semiconductor device as defined in claim 26, in which the stress relieving layer comprises a plurality of projections, and the conductive layer is formed to reach the projections;

wherein the second semiconductor device is the semiconductor device as defined in claim 26, in which the stress relieving layer comprises a plurality of projections, a plurality of recessed portions are formed between the adjacent projections, and the conductive layer is formed to reach the recessed portions; and

wherein the adjacent first and second semiconductor devices are electrically connected by the conductive layer, the projections in the first semiconductor device entering the recessed portions in the second semiconductor device.

41. The stack-type semiconductor device as defined in claim 37,

wherein an undermost semiconductor device is arranged so that the first surface of the semiconductor element faces other stacked semiconductor devices.

42. A circuit board over which is mounted the semiconductor device as defined in claim 24.

24. A semiconductor device comprising:

a semiconductor element having a through hole and a plurality of electrodes formed on a first surface of the semiconductor element;

a conductive layer which is electrically connected to the electrodes, and is provided from the first surface through an inner wall of the through hole to a second surface of the semiconductor element which is opposite to the first surface; and

a plurality of connecting portions provided on the conductive layer so that a distance between two connecting portions among the plurality of connecting portions is different from a distance between at least two electrodes among the plurality of electrodes, on at least one of the first and second surfaces.

43. An electronic instrument comprising the semiconductor device as defined in claim 24.