CIRCUIT FOR SIMULATING ZERO CUT-IN VOLTAGE DIODE AND RECTIFIER HAVING ZERO CUT-IN VOLTAGE CHARACTERISTIC

• US 20020030527A1
• Filed: 12/20/2000
• Published: 03/14/2002
• Est. Priority Date: 10/09/2000
• Status: Active Grant

• Current Assignee: Sunplus Technology Co., Ltd
• Original Assignee: Sunplus Technology Co., Ltd
• Inventors: Lee, Hsin Chou, Hung, Hsi-Hsien
• Granted Patent: US 6,404,268 B1
• Time in Patent Office: Days
• US Class Current: 327/309
• CPC Class Codes: H02M 7/217 using semiconductor devices only
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02M 7/2195 the switches being synchronously commutated at the same frequency of the AC input voltage
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

There is disclosed a circuit for simulating zero cut-in voltage diode and a rectifier having zero cut-in voltage characteristic. The MOS transistors manufactured by the CMOS process are used as circuit components and are properly biased so as to provide the rectifying capability, and thus are used as a rectifying diode. Furthermore, with a proper bias, the rectifying diode has zero cut-in voltage and a low current loss, and thus a high efficient rectifier can be implement.

Claims

1. A rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output, comprising:

a constant bias circuit having a resistor and a N-type MOS transistor, the N-type MOS transistor having a drain connected to the resistor and a gate connected to the drain;

a first N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode;

a second N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and

a first P-type MOS transistor and a second P-type MOS transistor connected in a cross couple structure which are coupled to the first and second N-type MOS transistors, whereby a high voltage level of the AC voltage input is applied to a high voltage level of the DC voltage output, and a low voltage level of the AC voltage input charges a low voltage level of the DC voltage output through one of the zero cut-in voltage diodes.

2. The rectifier as claimed in claim 1, wherein the first and second N-type MOS transistors and the N-type MOS transistor of the constant bias circuit have the same characteristic.

3. The rectifier as claimed in claim 1, wherein the N-type MOS transistor of the constant bias circuit is controlled by the resistor to be biased almost to a threshold voltage.

4. A circuit for simulating zero cut-in voltage diode comprising:

a first N-type MOS transistor having a gate and a drain connected together;

a resistor connected to the drain of the first N-type MOS transistor for forming a bias circuit; and

a second N-type MOS transistor with the same characteristic as the first N-type MOS transistor, having a gate connected to the gate of the first N-type MOS transistor;

wherein the first N-type MOS transistor is controlled by the resistor to be biased almost to a threshold voltage.

5. A rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output, comprising:

a constant bias circuit having a resistor and a P-type MOS transistor, the P-type MOS transistor having a drain connected to the resistor, and a gate connected to the drain;

a first P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode;

a second P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and

a first N-type MOS transistor and a second N-type MOS transistor connected in a cross couple structure which are coupled to the first and second P-type MOS transistors, whereby a low voltage level of the AC voltage input is applied to a low voltage level of the DC voltage output, and a high voltage level of the AC voltage input charges a high voltage level of the DC voltage output through one of the zero cut-in voltage diodes.

6. The rectifier as claimed in claim 5, wherein the first and second P-type MOS transistors and the P-type MOS transistor of the constant bias circuit have the same characteristic.

7. The rectifier as claimed in claim 6, wherein the P-type MOS transistor of the constant bias circuit is controlled by the resistor to be based to VDD−

Vtp, where VDD is the high voltage level of the DC voltage input and Vtp is a threshold voltage of the P-type MOS transistor.

8. A circuit for simulating zero cut-in voltage diode comprising:

a first P-type MOS transistor having a gate and a drain connected together;

a resistor connected to the drain of the first P-type MOS transistor, so as to form a bias circuit; and

a second P-type MOS transistor with the same characteristic as the first P-type MOS transistor, having a gate connected to the gate of the first P-type MOS transistor;

wherein the first P-type MOS transistor is controlled by the resistor to be based to VDD−

Vtp, where VDD represents a high voltage level of a DC voltage input and Vtp is a threshold voltage of the P-type MOS transistor.