Active load circuit, and operational amplifier and comparator having the same
First Claim
1. An active load circuit, comprising:
- first current mirror circuit for inputting input current of the one of differential input current to a first input terminal of current input transistors and for outputting output current of the one of differential output current from a first output terminal of current output transistors;
second current mirror circuit for inputting input current of the other of differential input current to a second input terminal of current input transistors and for outputting output current of the other of differential output current from a second output terminal of current output transistors;
first impedance circuit having one end connected to a reference potential connection terminal of the current input transistor in the first current mirror circuit and to the reference potential connection terminal of the current output transistor in the second current mirror circuit, and the other end connected to the reference potential; and
second impedance circuit having one end connected to the reference potential connection terminal of the current input transistor in the second current mirror circuit and to the reference potential connection terminal of the current output transistor in the first current mirror circuit, and the other end connected to the reference potential.
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Abstract
An active load circuit is provided, which is suitable for achieving an operational amplifier circuit, and which may cope with both output current capability and lower consumption current, with less offset, and may be capable of operating at higher speed in case of transient response. The active load circuit is comprised of MOS transistors Tr1 and Tr5 for forming a first current mirror circuit, MOS transistors Tr11 and Tr3 for forming a second current mirror circuit, and resistors R1 and R2. The sources of output transistors Tr5 and Tr11 of respective current mirror circuits are connected to the sources of input transistors Tr3 and Tr1 of the other current mirror circuits and then to the resistors R1 and R2. When the differential current component in the differential input stage becomes larger at the time of transient response of the operational amplifier, the bias current flowing through the next and following stages may be amplified, so that the high speed response characteristics in the transient response of the operational amplifier may be improved.
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Citations
16 Claims
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1. An active load circuit, comprising:
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first current mirror circuit for inputting input current of the one of differential input current to a first input terminal of current input transistors and for outputting output current of the one of differential output current from a first output terminal of current output transistors;
second current mirror circuit for inputting input current of the other of differential input current to a second input terminal of current input transistors and for outputting output current of the other of differential output current from a second output terminal of current output transistors;
first impedance circuit having one end connected to a reference potential connection terminal of the current input transistor in the first current mirror circuit and to the reference potential connection terminal of the current output transistor in the second current mirror circuit, and the other end connected to the reference potential; and
second impedance circuit having one end connected to the reference potential connection terminal of the current input transistor in the second current mirror circuit and to the reference potential connection terminal of the current output transistor in the first current mirror circuit, and the other end connected to the reference potential. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16)
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10. An operational amplifier, comprising:
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an active load circuit at the input differential stage, the active load circuit comprising;
first current mirror circuit for inputting input current of the one of differential input current to a first input terminal of current input transistors and for outputting output current of the one of differential output current from a first output terminal of current output transistors;
second current mirror circuit for inputting input current of the other of differential input current to a second input terminal of current input transistors and for outputting output current of the other of differential output current from a second output terminal of current output transistors;
first impedance circuit having one end connected to a reference potential connection terminal of the current input transistor in the first current mirror circuit and to the reference potential connection terminal of the current output transistor in the second current mirror circuit, and the other end connected to the reference potential; and
second impedance circuit having one end connected to the reference potential connection terminal of the current input transistor in the second current mirror circuit and to the reference potential connection terminal of the current output transistor in the first current mirror circuit, and the other end connected to the reference potential.
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Specification