Systems, processes and integrated circuits for improved packet scheduling of media over packet
First Claim
1. A method of processing first and second received packets of real-time information, comprising the steps of:
- computing for each of said received packets respective deadline intervals; and
ordering processing of the first and second received packets according to the respective deadline intervals.
1 Assignment
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Accused Products
Abstract
A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
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Citations
130 Claims
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1. A method of processing first and second received packets of real-time information, comprising the steps of:
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computing for each of said received packets respective deadline intervals; and
ordering processing of the first and second received packets according to the respective deadline intervals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 35)
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30. A method of processing packets from streams of real-time information in communications channels fed to buffers respective to the communications channesl and accumulating information in reserves in the buffers, comprising the steps of:
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computing for the buffers respective sizes of their respective reserves; and
ordering processing of the packets according to a priority depending at least in part on the sizes of the respective reserves. - View Dependent Claims (31, 32, 33, 34, 36, 37, 38, 40)
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39. A method of processing a received packet of real-time information, comprising the steps of:
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extracting a packet deadline for the received packet;
placing the packet in an egress scheduling list according to its deadline; and
updating the egress scheduling list as packets are utilized and as deadlines pass.
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41. A method of processing a received packet of real-time information, comprising the steps of:
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extracting a packet deadline interval DI of time-to-deadline for the received packet;
placing the packet in an egress scheduling list according to its deadline interval DI; and
updating the egress scheduling list by periodically decrementing the deadline interval DI for the packet. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
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52. A method of processing first and second received packets of real-time information from different communications channels, comprising the steps of:
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extracting a packet deadline interval DI of time-to-deadline for each received packet;
placing the packet in an egress scheduling list according to its deadline interval DI; and
decoding the packets according to a priority depending to their deadline intervals. - View Dependent Claims (53, 54)
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- 55. A method of processing first and second received packets of real-time information from different communications channels wherein the channels have decoders operating on non-coincident frame boundaries whereby a staggered-deadline process is executed, and wherein the first packet has a first deadline and is currently in decode while the second packet is just-arriving and has a second deadline earlier than the first deadline, and the process comprises testing to determine whether both the second and first packets can be decoded ahead of their respective deadlines if the second packet were decoded preemptively, and if so, then preempting processing the first packet and preemptively executing decode of the second packet.
- 60. A method of processing egress information and of executing an ingress process wherein the egress information has a value of lowest first deadline interval DI, and the method comprises preemption by the ingress process when the value of lowest first deadline interval DI of the egress information exceeds a predetermined amount K.
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63. A method of processing received packets of real-time information in channels having various channel deadlines Di, comprising:
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electronically putting values representative of the channel deadlines Di in an order of urgency;
launching decode execution of a first received packet having an early channel deadline;
detecting absence of a second packet having a second next most urgent channel deadline but presence of a third packet having a third next most urgent channel deadline;
launching decode execution said third packet whereupon the second packet arrives;
generating a value indicating whether sufficient time exists to save the second packet, and if so, then preempting the now-underway decode execution of the third packet to save the second packet. - View Dependent Claims (64, 65)
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66. A method of processing a packet stream of arriving packets having packetized information, the method comprising:
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detecting whether the arriving packets are respectively voice packets or silence packets;
queuing information from the voice packets;
decoding information from the voice packets to produce decoded voice information;
post-processing information from the silence packets; and
buffering the decoded voice information from the voice packets interspersed with post-processed information from the silence packets. - View Dependent Claims (67, 68, 69, 70, 71)
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72. A process of generating data descriptive of circular time differences between times of events A and B, the process comprising:
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electronically subtracting a value representative of the time of event B from a value representative of the time of event A, there resulting a most significant bit (MSB); and
providing the MSB itself as a flag indicating which of events A and B is prior to the other.
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73. A process of generating circular time differences between times of events A and B, the process comprising:
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electronically subtracting and delivering to a storage element a value representative of the time of event B from a value representative of the time of event A, resulting in an electronic representation (delta) having a most significant bit (MSB) and a sign bit S; and
electronically processing the electronic representation (delta) and a predetermined value (TMAX) in response to the MSB and the sign bit S to generate the circular time difference. - View Dependent Claims (74, 75, 76, 77, 78, 79, 80)
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81. A single-chip integrated circuit comprising:
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a processor circuit; and
embedded electronic instructions comprising an egress packet control establishing operations in the processor circuit generating for first and second received packets respective deadline intervals and ordering the processing in the processor circuit of the first and second received packets according to the respective deadline intervals.
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82. A single-chip stream processor integrated circuit adapted to process packets from streams of real-time information in communications channels, the single-chip stream processor comprising:
a processing unit; and
embedded electronic instructions comprising an egress packet control establishing egress channel buffers respective to the communications channels and further establishing operations in the processor unit streaming the packets to the channel buffers to accumulate information in reserves in the buffers, the operations establishing respective sizes of the respective reserves; and
ordering processing of the packets in the processing unit according to a priority depending at least in part on the sizes of the respective reserves.
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83. A single-chip integrated circuit comprising:
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a processor circuit; and
embedded electronic instructions comprising an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline interval DI of time-to-deadline for a received packet, that further place the packet in the egress scheduling list according to its deadline interval DI, and that periodically decrement the egress scheduling list deadline interval DI.
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84. A single-chip integrated circuit comprising:
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a processor circuit; and
embedded electronic instructions comprising an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals DI, place packets in the egress scheduling list according to deadline intervals DI; and
embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
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85. A single-chip integrated circuit comprising:
a processor circuit; and
embedded electronic instructions comprising an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that establish channel decoders on non-coincident frame boundaries and a packet engine to detect when a first packet has a first deadline and is currently in decode while a second packet is just-arriving and has a second deadline earlier than the first deadline, and the packet engine establishes a determination whether both the second and first packets can be decoded ahead of their respective deadlines if the second packet were decoded preemptively, and if so, then preempts the processor circuit channel decoder structure to decode the second packet.
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86. A single-chip integrated circuit comprising:
a processor circuit; and
embedded electronic instructions comprising an ingress/egress packet control engine that processes egress information and determines lowest first egress deadline interval DI and further executes an ingress process preempting the egress process when the value of lowest first egress deadline interval DI exceeds a predetermined amount K.
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87. A single-chip integrated circuit comprising:
a processor circuit; and
embedded electronic instructions comprising an ingress/egress packet control engine that processes egress channels having various channel deadlines Di, electronically orders channel deadlines Di by urgency, decodes a first egress packet having a deadline, detects absence of a second packet having a second next most urgent channel deadline but presence of a third packet having a third next most urgent channel deadline, launches decode of said third packet, and whereupon the second packet arrives, generates a value indicating whether sufficient time exists to save the second packet, and if so, preempts the now-underway decode execution of the third packet to save the second packet.
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88. A single-chip integrated circuit comprising:
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a processor circuit; and
embedded electronic instructions comprising an egress packet control engine that detects whether the arriving packets are respectively voice packets or silence packets, queues information from the voice packets and produces decoded voice information, post-processes the silence packets, and buffers the decoded voice information from the voice packets interspersed with post-processed silence packets.
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89. A single-chip integrated circuit comprising:
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storage for values representative of the time of two events;
a subtractor coupled to the storage and operative to generate a difference value (delta) and deliver the difference value into said storage thereby resulting a most significant bit (MSB) of the difference value (delta); and
a flag register having a bit fed with said MSB to indicating which of events A and B is prior to the other.
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90. A single-chip circular time differencing integrated circuit comprising:
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storage for values representative of the time of two events;
an adder/subtractor coupled to the storage and operative to generate an electronic difference (delta) and deliver the difference value into said storage thereby resulting a sign bit (S) and a most significant bit (MSB) of the difference value (delta); and
logic circuitry responsive to the MSB and the sign bit S of the electronic difference (delta) and a predetermined value (TMAX), the logic circuitry driving said adder/subtractor to generate the circular time difference of the two events. - View Dependent Claims (91)
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92. A wireless telephone comprising an antenna, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the antenna, said at least one integrated circuit assembly providing voice over packet transmissions and embedded electronic instructions comprising an egress packet control establishing an egress scheduling list structure and operations in the integrated circuit that extract a packet deadline interval DI of time-to-deadline for a received packet, that further place the packet in the egress scheduling list according to its deadline interval DI, and that periodically decrement the egress scheduling list deadline interval DI.
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93. A wireless telephone comprising an antenna, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the antenna, said at least one integrated circuit assembly providing voice over packet transmissions and embedded electronic instructions comprising an egress packet control that generates for first and second received packets respective deadline intervals and orders the processing in the processor circuit of the first and second received packets according to the respective deadline intervals.
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94. A wireless telephone comprising an antenna, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the antenna, said at least one integrated circuit assembly providing voice over packet transmissions and embedded electronic instructions comprising an egress packet control establishing an egress scheduling list structure and operations in the integrated circuit that extract a packet deadline intervals DI, place packets in the egress scheduling list according to deadline intervals DI;
- and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
- 95. A wireless telephone comprising an antenna, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the antenna, said at least one integrated circuit assembly providing voice over packet transmissions and embedded electronic instructions comprising an ingress/egress packet control that processes egress information and determines lowest first egress deadline interval DI and further executes an ingress process preempting the egress process when the value of lowest first egress deadline interval DI exceeds a predetermined amount K.
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99. A wireless telephone comprising an antenna, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the antenna, said at least one integrated circuit assembly providing voice over packet transmissions and embedded electronic instructions comprising an egress packet control establishing an egress scheduling list structure and operations in the integrated circuit that detects whether the arriving packets are respectively voice packets or silence packets, queues information from the voice packets and produces decoded voice information, post-processes the silence packets, and buffers the decoded voice information from the voice packets interspersed with post-processed silence packets.
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100. A wireless telephone comprising an antenna, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the antenna, said at least one integrated circuit assembly generating data descriptive of circular time differences between times of events A and B by electronically subtracting a value representative of the time of event B from a value representative of the time of event A, there resulting a most significant bit (MSB);
- and providing the MSB itself as a flag indicating which of events A and B is prior to the other.
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101. A wireless telephone comprising an antenna, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the antenna, said at least one integrated circuit assembly generating circular time differences between times of events A and B by electronically subtracting and delivering to a storage element a value representative of the time of event B from a value representative of the time of event A, resulting in an electronic representation (delta) having a most significant bit (MSB) and a sign bit S;
- and electronically processing the electronic representation (delta) and a predetermined value (TMAX) in response to the MSB and the sign bit S to generate the circular time difference.
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102. An information storage article of manufacture comprising:
a storage medium holding physical variations representing bits of information; and
said bits of information comprising processing instructions for first and second received packets of real-time information, computing for each of said received packets respective deadline intervals; and
ordering processing of the first and second received packets according to the respective deadline intervals.- View Dependent Claims (103, 104, 105, 106, 107)
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108. A real-time packet networking appliance comprising:
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a network interface;
a voice transducer; and
at least one integrated circuit assembly coupling the voice transducer to the network interface, said at least one integrated circuit assembly providing real-time packet transmissions and embedded electronic instructions comprising an egress packet control establishing operations in the processor circuit generating for first and second received packets respective deadline intervals and ordering the processing in the processor circuit of the first and second received packets according to the respective deadline intervals. - View Dependent Claims (109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 121, 122, 123, 124, 128, 129, 130)
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120. A computer comprising
A network interface; -
an audio reception transducer;
an audio emission transducer; and
at least one integrated circuit assembly coupling the audio reception transducer and audio emission transducer to the network interface, said at least one integrated circuit assembly providing voice over packet transmission and reception and including an egress packet control generating for first and second received packets respective deadline intervals and ordering the processing in the processor circuit of the first and second received packets according to the respective deadline intervals.
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125. A private branch exchange comprising
telephone interface circuitry having plural connectors ready for connection to plural telephone units; -
a digital network interface ready for connection to PSTN (public switched telephone network); and
at least one integrated circuit assembly coupling the telephone interface circuitry to the digital network interface, said at least one integrated circuit assembly providing voice over packet transmission and reception and including egress packet control of voice packets generating for first and second received packets respective deadline intervals and ordering the processing in the integrated circuit assembly of the first and second received packets according to the respective deadline intervals.
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126. A wireless base station comprising
cellular telephone wireless transmit/receive interface circuitry for communication with cell telephone handsets in the vicinity of the wireless base station; -
a packet network interface; and
at least one integrated circuit assembly coupling the cellular telephone wireless transmit/receive interface circuitry to the packet network interface, said at least one integrated circuit assembly providing voice over packet transmission and reception and including an egress packet control of voice packets generating for first and second received packets respective deadline intervals and ordering the processing in the integrated circuit assembly of the first and second received packets according to the respective deadline intervals.
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127. A computer add-in card comprising:
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a processor circuit;
an egress packet control generating for first and second received packets respective deadline intervals and ordering the processing in the integrated circuit assembly of the first and second received packets according to the respective deadline intervals;
a printed wiring board bearing said processor circuit and egress packet control, said printed wiring board having an output connector for passage of packets and diversity packets therethrough from said processor and said printed wiring board further having an insertion connector, whereby the printed wiring board is insertable via the insertion connector.
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Specification