Method of managing voice buffers in dynamic bandwidth circuit emulation services

• US 20020031129A1
• Filed: 09/10/2001
• Published: 03/14/2002
• Est. Priority Date: 09/13/2000
• Status: Abandoned Application

• Current Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Original Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Inventors: Jeffrey, George, Finn, Dawn
• Application Number:
  US09/948,651
• Publication Number:
  US 20020031129A1
• Time in Patent Office: Days
• US Class Current: 370/395.41
• CPC Class Codes: H04L 12/6418 Hybrid transport
• CPC Class Codes: H04L 2012/5654 using the AAL1
• CPC Class Codes: H04L 2012/5671 Support of voice
• CPC Class Codes: H04L 2012/5681 Buffer or queue management

Abstract

In a method of managing buffers in a SAR (Segmentation and Reassembly) device operating in DBCES (Dynamic Bandwidth Circuit Emulation Service) mode, first an active channel buffer limit is determined. This is dependent on the number of active channels in the virtual circuit. Next, the amount of buffering for each active channel is set equal to the CDV (Cell Delay Variation) plus the active channel buffer limit. This prevents underruns over overruns from occurring when the number of active channels suddenly changes.

Claims

1. A method of managing buffers in a SAR (Segmentation and Reassembly) device operating in DBCES (Dynamic Bandwidth Circuit Emulation Service) mode, comprising:

determining an active channel buffer limit for a virtual circuit dependent on the number of active channels; and

setting the amount of buffering for each active channel equal to the CDV (Cell Delay Variation) plus the active channel buffer limit.

2. A method as claimed in claim 1, wherein each buffer has a write-pointer and a read-pointer, and the distance between the write-pointer and the read-pointer determines the amount of buffering.

3. A method as claimed in claim 1, wherein the active channel buffer limit is equal to the number of bytes of payload data per cell divided by the minimum number of allowable channels less the number of bytes of payload data per cell divided by the number of current active channels.

4. A method as claimed in claim 3, wherein the amount of buffering is recalculated when the number of channels changes so as to provide adequate buffering the next time a change in the number of channels occurs.

5. A method as claimed in claim 4, wherein said method can be activated by setting a control bit in a control structure for the buffers.

6. A method as claimed in claim 4, wherein said buffers are circular buffers.

7. A method as claimed as claimed in claim 1, wherein said DBCES is implemented in an ATM network.

8. A control data structure for a SAR (Segmentation and Reassembly) device capable of implementing DBCES (Dynamic Bandwidth Circuit Emulation Service) mode, comprising:

a control field having a bit determining whether buffer management is active; and

bits determining the minimum buffering for each channel; and

wherein

the amount of buffering for each active channel is set equal to the CDV (Cell Delay Variation) less active channel buffer limit, which is dependent on the number of active channels.

9. A control data structure as claimed in claim 8, wherein the active channel buffer limit is equal to the number of bytes of payload data per cell divided by the minimum number of allowable channels less the number of bytes of payload data per cell divided by the number of current active channels.

10. A control data structure as claimed in claim 8, wherein the active channel limit 47/MIN, where MIN is the minimum number of channels N contemplated, minus 47/N, where N is the number of current active channels.