Transmitter, receiver and transceiver arrangement

• US 20020031219A1
• Filed: 07/17/2001
• Published: 03/14/2002
• Est. Priority Date: 07/18/2000
• Status: Abandoned Application

• Current Assignee: Technische Universitã¤T Berlin (Tu)
• Original Assignee: Technische Universitã¤T Berlin (Tu)
• Inventors: Gutsche, Jan, Schoppa, Irenaeus
• Application Number:
  US09/907,115
• Publication Number:
  US 20020031219A1
• Time in Patent Office: Days
• US Class Current: 380/28
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 2209/34 Encoding or coding, e.g. Huffman coding or error correction
• CPC Class Codes: H04L 9/0662 with particular pseudorandom sequence generator

Abstract

A transmitter, a receiver and a combined transceiver arrangement (50) exchange data with external devices through a serial transmission channel. According to this invention, the transmitter (52) comprises encoding means (60, 64, 68, 70), and the receiver (54) comprises decoding means (60, 74, 76, 80). The invention is explained in detail using a design example of a crypt UART component (50).

Claims

1. A transmitter for transmitting data of a first type consisting of binary-coded, serial data, the transmitter comprising

a data input designed to receive data of a pre-determined second type,

a data converter, connected with the data input, to convert the data of the second type into data of the first type, and

a data output, connected with the data converter. to release data of the first type, characterized by a means for encoding data of the first type into encoded data of the same type, located between the data converter and the data output.

2. The transmitter of claim 1, wherein the data converter comprises:

a transmit shift register connected with the encoding means for receiving binary-coded data and serially releasing binary-coded data.

3. The transmitter of claim 2, wherein the encoding means comprises:

a key register for receiving and releasing an adjustable binary key with a pre-determined number of bit positions.

4. The transmitter of claim 1, wherein the encoding means comprises:

a key register for receiving and releasing an adjustable binary key with a pre-determined number of bit positions.

5. The transmitter of claim 4, wherein the key register is connected with data input.

6. The transmitter of claim 3, wherein the key register is connected with data input.

7. The transmitter of claim 5, wherein the encoding means comprises:

an encoding element, connected on an input side thereof with the data converter, for encoding data received therefrom.

8. The transmitter of claim 6, wherein the encoding means comprises:

an encoding element, connected on an input side thereof with the data converter, for encoding data received therefrom.

9. The transmitter of claim 7, wherein the encoding element is connected on the input side with the key register.

10. The transmitter of claim 8, wherein the encoding element is connected on the input side with the key register.

11. The transmitter of claim 9, wherein the encoding means comprises:

a pseudo-random sequence generator for the generating and releasing a binary-coded pseudo-random sequence.

12. The transmitter of claim 10, wherein the encoding means comprises:

a pseudo-random sequence generator for the generating and releasing a binary-coded pseudo-random sequence.

13. The transmitter of claim 11, wherein the pseudo-random sequence generator is connected on an output side thereof with the encoding element.

14. The transmitter of claim 12, wherein the pseudo-random sequence generator is connected on an output side thereof with the encoding element.

15. The transmitter of claim 13, wherein the pseudo-random sequence generator is connected on an input side thereof with the key register.

16. The transmitter of claim 14, wherein the pseudo-random sequence generator is connected on an input side thereof with the key register.

19. The receiver of claim 18, wherein the data converter comprises:

a receive shift register to serially receive and release binary-coded data.

20. The receiver of claim 18, wherein the decoding means comprises:

a key register for receiving an adjustable binary key with a pre-determined number of bit positions.

21. The receiver of claim 19, wherein the decoding means comprises:

a key register for receiving an adjustable binary key with a pre-determined number of bit positions.

22. The receiver of claim 20, wherein the key register is connected with the data input.

23. The receiver of claim 21, wherein the key register is connected with the data input.

24. The receiver of claim 20, wherein the key register is connected with the data output.

25. The receiver of claim 21, wherein the key register is connected with the data output.

26. The receiver of claim 22, wherein the key register is connected with the data output.

27. The receiver of claim 23, wherein the key register is connected with the data output.

28. The receiver of claim 18, wherein the decoding means comprises:

a decoding element, connected on an output side thereof with the data converter, for decoding data received from the data input.

29. The receiver of claim 24, wherein the decoding means comprises:

a decoding element, connected on an output side thereof with the data converter, for decoding data received from the data input.

30. The receiver of claim 25, wherein the decoding means comprises:

a decoding element, connected on an output side thereof with the data converter, for decoding data received from the data input.

31. The receiver of claim 26, wherein the decoding means comprises:

a decoding element, connected on an output side thereof with the data converter, for decoding data received from the data input.

32. The receiver of claim 27, wherein the decoding means comprises:

a decoding element, connected on an output side thereof with the data converter, for decoding data received from the data input.

33. The receiver of claim 29, wherein the decoding element is connected on an input side thereof with the key register.

34. The receiver of claim 30, wherein the decoding element is connected on an input side thereof with the key register.

35. The receiver of claim 31, wherein the decoding element is connected on an input side thereof with the key register.

36. The receiver of claim 32, wherein the decoding element is connected on an input side thereof with the key register.

37. The receiver of claim 18, wherein the decoding means comprises a pseudo-random sequence generator to generate and release a binary-coded pseudo-random sequence.

38. The receiver of claim 35, wherein the decoding means comprises a pseudo-random sequence generator to generate and release a binary-coded pseudo-random sequence.

39. The receiver of claim 36, wherein the decoding means comprises a pseudo-random sequence generator to generate and release a binary-coded pseudo-random sequence.

40. The receiver of claim 34, wherein the decoding means comprises a pseudo-random sequence generator to generate and release a binary-coded pseudo-random sequence.

41. The receiver of claim 33, wherein the decoding means comprises a pseudo-random sequence generator to generate and release a binary-coded pseudo-random sequence.

42. The receiver of claim 37, wherein the pseudo-random sequence generator is connected on an output side thereof with the de coding element.

43. The receiver of claim 38, wherein the pseudo-random sequence generator is connected on an output side thereof with the decoding element.

44. The receiver of claim 39, wherein the pseudo-random sequence generator is connected on an output side thereof with the decoding element.

45. The receiver of claim 40, wherein the pseudo-random sequence generator is connected on an output side thereof with the decoding element.

46. The receiver of claim 41, wherein the pseudo-random sequence generator is connected on an output side thereof with the decoding element.

47. The receiver of claim 43, wherein the pseudo-random sequence generator is connected on an input side thereof with the key register.

48. The receiver of claim 44, wherein the pseudo-random sequence generator is connected on an input side thereof with the key register.

49. The receiver of claim 45, wherein the pseudo-random sequence generator is connected on an input side thereof with the key register.

50. The receiver of claim 46, wherein the pseudo-random sequence generator is connected on an input side thereof with the key register.

51. The transmitter of claim 16, further comprising:

a crypt control register connected on an output side thereof with the encoding element to receive and release of binary-coded control data.

52. The receiver of claim 48, further comprising:

a crypt control register connected, on an output side thereof with the decoding element to receive and release of binary-coded control data.

53. The transmitter of claim 51, wherein the crypt control register is connected with the key register.

54. The receiver of claim 52, wherein the crypt control register is connected with the key register.

55. The transmitter of claim 53, wherein the crypt control register is connected with the pseudo-random sequence generator.

56. The receiver of claim 54, wherein the crypt control register is connected with the pseudo-random sequence generator.

57. The transmitter of claim 55, wherein the pseudo-random sequence generator comprises:

a sequence generator circuit having a regenerative shift register with a feedback circuit.

58. The receiver of claim 56, wherein the pseudo-random sequence generator comprises:

a sequence generator circuit having a regenerative shift register with a feedback circuit.

59. The transmitter of claim 57, wherein the feedback circuit defines a linear feedback function.

61. The transmitter of claim 57, wherein the feedback circuit defines a feedback function that is a primitive polynomial modulo two.

62. The receiver of claim according to claim 58, wherein the feedback circuit defines a feedback function that is a primitive polynomial modulo two.

63. The transmitter of claim 57, wherein the shift register of the sequence generator circuit is designed so that a part of the shift register simultaneously assumes the function of the key register.

64. The receiver of claim 58, wherein the shift register of the sequence generator circuit is designed so that a part of the shift register simultaneously assumes the function of the key register.

65. The transmitter of claim 63, wherein the shift register of the sequence generator circuit comprises at least a first and a last sub-register connected in series for chronologically parallel reception of a part of the binary key consisting of a pre-determined number of bit positions, where the las sub-register in sequence provides a serial release of the part of the binary key contained therein, and the other sub-registers provide a chronologically parallel release of the part of the binary key contained in each of them to the sub-register that follows in sequence.

66. The receiver of claim 64, wherein the shift register of the sequence generator circuit comprises at least a first and a last sub-register connected in series for chronologically parallel reception of a part of the binary key consisting of a pre-determined number of bit positions, where the las sub-register in sequence provides a serial release of the part of the binary key contained therein, and the other sub-registers provide a chronologically parallel release of the part of the binary key contained in each of them to the sub-register that follows in sequence.

67. The transmitter of claim 65, wherein the shift register of the sequence generator circuit comprises at least a first and a last flip-flop connected in series so that the first flip-flop first in sequence is assigned the highest-value bit position, the second flip-flop connected on an input side therof with an output of the first flip-flop is assigned the next lower-value bit position, and so forth until the last flip-flop is assigned the least-value (“

least significant”

) bit position.

68. The receiver of claim 66, wherein the shift register of the sequence generator circuit comprises at least a first and a last flip-flop connected in series so that the first flip-flop first in sequence is assigned the highest-value bit position, the second flip-flop connected on an input side therof with an output of the first flip-flop is assigned the next lower-value bit position, and so forth until the last flip-flop is assigned the least-value (“

least significant”

) bit position.

69. The transmitter of claim 67, wherein the sequence generator circuit comprises:

a first XOR gate that follows the last flip-flop of the shift register, with at least two inputs thereof connected to the outputs of pre-determined flip-flops, and with an output connected with the input of the first flip-flop and with the data output of the transmitter.

70. The receiver of claim according to claim 68, wherein the sequence generator circuit comprises:

a first XOR gate that follows the last flip-flop of the shift register, with at least two inputs thereof connected to the outputs of predetermined flip-flops, and with an output connected with the input of the first flip-flop and with the receive shift register of the receiver.

71. The transmitter of claim 69, wherein that the sequence generator circuit comprises:

a 64-bit shift register, where the outputs of the first flip-flop, of the penultimate flip-flop and of the last flip-flop are connected with the first XOR gate.

72. The transmitter of claim 69, wherein that the sequence generator circuit comprises:

a 64-bit shift register, where the outputs of the first flip-flop, of the penultimate flip-flop and of the last flip-flop are connected with the first XOR gate.

73. The transmitter of claim 69, wherein the sequence generator circuit comprises:

a 63-bit shift register where the outputs of the first flip-flop, of the fifty seventh flip-flop, of the fifty eighth flip-flop, of the sixtieth flip-flop and of the sixty third flip-flop thereof are each connected with one input of a second XOR gate, and

the output of the second XOR gate is connected with the data output of the transmitter.

74. The receiver of claim 70, wherein the sequence generator circuit comprises:

a 63-bit shift register where the outputs of the first flip-flop, of the fifty seventh flip-flop, of the fifty eighth flip-flop, of the sixtieth flip-flop and of the sixty third flip-flop thereof are each connected with one input of a second XOR gate, and

the output of the second XOR gate is connected with the receive shift register of the receiver.

75. The transmitter of claim 73, wherin the sequence generator circuit comprises:

a third XOR gate, to whose inputs are connected the output of the first XOR gate and the output of the second XOR gate,

where the output of the third XOR gate is connected with the data output of the transmitter.

76. The receiver of claim 74, wherin the sequence generator circuit comprises:

a third XOR gate, to whose inputs are connected the output of the first XOR gate and the output of the second XOR gate,

where the output of the third XOR gate is connected with the receive shift register of the receiver.

77. The transmitter of claim 75, wherein the encoding element comprises:

a fourth XOR gate to whose inputs are connected the output of the third XOR gate and the data converter of the transmitter, and whose output is connected with the data output of the transmitter.

78. The receiver of claim 76, wherein the decoding element comprises:

a fourth XOR gate to whose inputs are connected the output of the third XOR gate and the data input of the receiver, and whose output is connected with the data converter of the receiver.

79. The transmitter of claim 77, further comprising:

a baud rate generator that is connected on an output side thereof, in a parallel arrangement with the data converter and the encoding means to generate and release a timing signal with a pre-determinable frequency.

80. The receiver of claim 78, further comprising:

a baud rate generator that is connected on an output side therof, in a parallel arrangement with the data converter and the decoding means to generate and release a timing signal with a pre-determinable frequency.

81. The transmitter of claim 79, comprising:

a sequence generator circuit, the operation of which is activated or deactivated by a control bit contained in the crypt control register.

82. The receiver of claim 80, comprising:

a sequence generator circuit, the operation of which is activated or deactivated by a control bit contained in the crypt control register.

83. The transmitter of claim 81, wherein the key register is circuited so that the write access to the key register is activated or deactivated by a control bit contained in the crypt control register.

84. The receiver of claim 82, wherein the key register is circuited so that the write access to the key register is activated or deactivated by a control bit contained in the crypt control register.

85. The transmitter of claim 61, wherein its components are integrated in a transmitter component.

86. The receiver of claim 62, wherein its components are integrated in a receiver component.

17. A transmitter for transmitting data of a first type consisting of binary-coded, serial data, the transmitter comprising

a data input designed to receive data of a pre-determined second type,

a data converter, connected with the data input, to convert the data of the second type into data of the first type, the data converter comprising a transmit shift register connected with the encoding means for receiving binary-coded data and serially releasing binary-coded data;

and

a data output, connected with the data converter. to release data of the first type, characterized by a means for encoding data of the first type into encoded data of the same type, located between the data converter and the data output.;

the encoding means comprising a key register for receiving and releasing an adjustable binary key with a pre-determined number of bit positions;

the key register being connected with data input;

the encoding means further comprising an encoding element, connected on an input side thereof with the data converter, for encoding data received therefrom.

the encoding element further connected on the input side with the key register;

the encoding means further comprising a pseudo-random sequence generator for the generating and releasing a binary-coded pseudo-random sequence.

the pseudo-random sequence generator being connected on an output side thereof with the encoding element; and

the pseudo-random sequence generator further connected on an input side thereof with the key register.

18. A receiver for receiving data of a first type containing binary-coded, serial data, the receiver comprising:

a data input for receiving data of the first type;

a data converter connected with the data input for convert data of the first type into data of a second type;

a data output connected with the data converter for releasing data of the second type, characterized by a means for decoding to convert encoded data of the first type into non-encoded data of the first type, located between the data input and the data converter.

60. The receiver of claim, wherein the feedback circuit defines a linear feedback function.

87. A transceiver arrangement, comprising:

a transmitter unit for transmitting data of a first type consisting of binary-coded, serial data, comprising;

a data input designed to receive data of a pre-determined second type,

a data converter, connected with the data input, to convert the data of the second type into data of the first type, the data converter comprising a transmit shift register connected with the encoding means for receiving binary-coded data and serially releasing binary-coded data; and

a data output, connected with the data converter. to release data of the first type, characterized by a means for encoding data of the first type into encoded data of the same type, located between the data converter and the data output.;

the encoding means comprising a key register for receiving and releasing an adjustable binary key with a pre-determined number of bit positions;

the key register being connected with data input;

the encoding means further comprising an encoding element, connected on an input side thereof with the data converter, for encoding data received therefrom.

the encoding element further connected on the input side with the key register;

the encoding means further comprising a pseudo-random sequence generator for the generating and releasing a binary-coded pseudo-random sequence.

the pseudo-random sequence generator being connected on an output side thereof with the encoding element; and

the pseudo-random sequence generator further connected on an input side thereof with the key register, and

a receiver unit for receiving data of a first type containing binary-coded, serial data, comprising;

a data input for receiving data of the first type;

a data converter connected with the data input for convert data of the first type into data of a second type, comprising a receive shift register to serially receive and release binary-coded data;

a data output connected with the data converter for releasing data of the second type, characterized by a means for decoding to convert encoded data of the first type into non-encoded data of the first type, located between the data input and the data converter;

the decoding means comprising a key register for receiving an adjustable binary key with a pre-determined number of bit positions;

the key register being connected with the data input;

the decoding means further comprising a decoding element, connected on an output side thereof with the data converter, for decoding data received from the data input;

the decoding element being connected on an input side thereof with the key register;

the decoding means further comprising a pseudo-random sequence generator to generate and release a binary-coded pseudo-random sequence;

the pseudo-random sequence generator being connected on an output side thereof with the decoding element; and

the pseudo-random sequence generator being connected on an input side thereof with the key register.

88. The transceiver arrangement of claim 87, wherein the data input of the transmitter unit is designed for the reception of binary-coded (parallel) data structures containing several chronologically parallel proceeding bit positions, that the data converter of the transmitter unit is a parallel/serial converter designed to convert a parallel data structure into serial data, and that the data converter of the receiver unit is a serial/parallel converter designed to convert serial data into a parallel data structure.

89. The transceiver arrangement of claim 88, comprising:

a UART (Universal Asynchronous Receiver Transmitter) component.

90. The transceiver arrangement of claim 89, comprising:

a register record and a control data record, which contains all register and control data of a type PC16550D UART component.

91. The transceiver arrangement of claim 90, characterized by an addressing of the key register and the crypt control register in a read mode and a write mode compatible with a PC16550D type UART component.

92. A receiver for receiving data of a first type containing binary-coded, serial data, the receiver comprising:

a data input for receiving data of the first type;

a data converter connected with the data input for convert data of the first type into data of a second type, comprising a receive shift register to serially receive and release binary-coded data;

a data output connected with the data converter for releasing data of the second type, characterized by a means for decoding to convert encoded data of the first type into non-encoded data of the first type, located between the data input and the data converter;

the decoding means comprising a key register for receiving an adjustable binary key with a pre-determined number of bit positions;

the key register being connected with the data input;

the decoding means further comprising a decoding element, connected on an output side thereof with the data converter, for decoding data received from the data input;

the decoding element being connected on an input side thereof with the key register;

the decoding means further comprising a pseudo-random sequence generator to generate and release a binary-coded pseudo-random sequence;

the pseudo-random sequence generator being connected on an output side thereof with the decoding element;

the pseudo-random sequence generator being connected on an input side thereof with the key register.