Method of fabrication of stacked semiconductor devices

• US 20020031864A1
• Filed: 08/30/2001
• Published: 03/14/2002
• Est. Priority Date: 05/20/1996
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Michael B. Ball
• Inventors: Ball, Michael B.
• Granted Patent: US 6,784,023 B2
• Time in Patent Office: Days
• US Class Current: 438/113
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A method for increasing integrated circuit density comprising stacking an upper wafer and a lower wafer, each of which have fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complimentary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be diced into individual die pairs or wafer portions containing more than one die pair.

Claims

1. A method of fabricating a multi-level stack of semiconductor substrate elements, each of said elements including integrated circuitry, comprising:

providing a first semiconductor substrate element having a first side including integrated circuitry thereon and having a back side;

providing at least one second semiconductor substrate element having a first side including a plurality of integrated circuitry thereon and having a backside;

stacking said first semiconductor element and said at least one second semiconductor substrate element in a superimposed relationship having the back side of the first semiconductor substrate element facing the back side of the at least one second semiconductor substrate element aligning vertically said first semiconductor substrate element and the at least one second semiconductor substrate element to vertically align integrated circuitry on said first semiconductor substrate element and at least one of the plurality of integrated circuits on said at least one semiconductor substrate element; and

severing from said stack traversely at least one dice pair comprising a die from said first semiconductor substrate element and an aligned second die from said at least one second semiconductor substrate element; and

adhesively attaching said first semiconductor substrate element and said at least one second semiconductor substrate element.

2. The method of claim 1, wherein said adhesive comprises a dielectric adhesive.

3. The method of claim 1, further including:

disposing a heat sink element between said first semiconductor substrate element and said at least one second semiconductor substrate element.

4. The method of claim 1, wherein said first substrate element and at least one second semiconductor substrate element, each element including locations defining discrete dice or wafer portions severable from a first semiconductor substrate wafer and at least one second substrate wafer.

5. The method of claim 1, wherein said first semiconductor substrate element and the at least one second semiconductor substrate element each include a flat, and said vertical alignment is effected by aligning said flat of said first semiconductor substrate element and said flat of the at least one second semiconductor substrate element.

6. The method of claim 1, further comprising:

connecting a first die of said at least one dice pair to conductors of a substrate.

7. The method of claim 6, wherein said connection is selected from a group comprising reflowable metal elements, polymer elements having a conductive capability, and preformed lead-type elements.

8. The method of claim 6, further comprising:

connecting both dice of said at least one dice pair to conductors of said substrate.

9. The method of claim 1, further comprising:

connecting the second die of said at least one dice pair to conductors of said substrate through intermediate connection elements.

10. The method of claim 1, wherein said intermediate connection elements are selected from a group consisting of bond wires and traces of flex circuits.

11. The method of claim 10, further comprising:

connecting said at least one dice pair to conductors of a substrate and encapsulating said at least one dice pair there after.

13. The method of claim 12, further including:

stacking said semiconductor wafer segments of said at least one semiconductor wafer segment stack with the integrated circuitry side of said first semiconductor wafer segment proximate the back side of said at least one second semiconductor wafer segment; and

locating said bond pads on said integrated circuitry side of said first semiconductor wafer segment.

14. The method of claim 12, further including:

adhesively attaching said first and said at least one second semiconductor wafer segments of said at least one semiconductor wafer segment stack.

15. The method of claim 12, further including disposing a heat sink element between said first and said at least one second semiconductor wafer segments.

16. The method of claim 12, further comprising:

connecting at least one of said first and said at least one second semiconductor wafer segment to conductors of a substrate.

17. The method of claim 16, wherein said connection comprises a connection element selected from a group comprising bond wires and traces of flex circuits.

19. The method of claim 18, further including:

stacking said first semiconductor wafer and said at least one other semiconductor wafer with a third semiconductor wafer, having the integrated circuitry side of said first semiconductor wafer segment proximate the back side of said third semiconductor wafer.

20. The method of claim 18, wherein said adhesively attaching said first semiconductor wafer and said at least one other semiconductor wafer comprises:

adhesively attaching said first semiconductor wafer and said at least one other semiconductor wafer with a dielectric adhesive.

21. The method of claim 18, further including:

disposing a heat sink element between said first semiconductor wafer and said at least one other semiconductor wafer.

22. The method of claim 18, further comprising:

connecting at least one of said first semiconductor wafer and said at least one other semiconductor wafer to conductors of a substrate.

23. The method of claim 22, wherein a direct electrical connection is achieved with a connection element selected from a group comprising bond wires and traces of flex circuits.

24. The method of claim 18, wherein said first semiconductor wafer and said at least one other semiconductor wafer are stacked with the integrated circuit side of said first semiconductor wafer facing the back side of said at least one other semiconductor wafer, and wherein said bond pads are located on the integrated circuit side of said first semiconductor wafer.

12. A method of fabricating a multi-level stack of semiconductor wafer segments, each of said semiconductor wafer segments including integrated circuitry, comprising:

providing a first semiconductor substrate segment having a first side including integrated circuitry thereon and having a back side;

providing at least one second semiconductor substrate segment having a first side including a plurality of integrated circuits thereon and having a backside;

stacking said first semiconductor substrate segment and said at least one second semiconductor substrate wafer in at least partially superimposed relationship to form a stack of semiconductor wafer segment;

separating said stack to form at least two semiconductor wafer segment stacks, each said semiconductor wafer segment stack comprising a first semiconductor wafer segment having a side including integrated circuitry and a back side and at least one second semiconductor wafer segment having a side including integrated circuitry and a back side,

stacking said at least two semiconductor wafer segment stacks in at least partially superimposed relationship;

locating bond pads on said first semiconductor wafer segment of at least one of said at least two semiconductor wafer segment stacks on the side adjacent said at least one second semiconductor wafer segment of said at least one semiconductor wafer segment stack at a periphery thereof;

forming a notch through said at least one second semiconductor wafer segment of said at least one semiconductor wafer segment stack, said notch extending between and substantially perpendicular to a circuitry side and a back side of said at least one second semiconductor wafer segment to provide access to at least one said peripheral bond pad of said first semiconductor wafer segment of said at least one semiconductor wafer segment stack; and

adhesively attaching said first and said at least one second semiconductor wafer segments of said at least one semiconductor wafer segment stack.

18. A method of fabricating a multi-level stack of semiconductor wafers, each of said semiconductor wafers including integrated circuitry, comprising:

providing a first semiconductor wafer having a first side including integrated circuitry and having a back side;

providing at least one other semiconductor wafer having a first side including integrated circuitry and having a back side;

stacking said first semiconductor wafer and said at least one other semiconductor wafer in a superimposed relationship;

locating bond pads on said first semiconductor wafer of said stack on the side proximate said at least one other semiconductor wafer at a periphery thereof;

forming a notch through said at least one other semiconductor wafer, said notch substantially perpendicular to a circuitry side and a back side of said at least one other semiconductor wafer providing access to at least one said peripheral bond pads of said first semiconductor wafer of said stack; and

adhesively attaching said first semiconductor wafer and said at least one other semiconductor wafer.