Method of fabrication of stacked semiconductor devices
First Claim
1. A method of fabricating a multi-level stack of semiconductor substrate elements, each of said elements including integrated circuitry, comprising:
- providing a first semiconductor substrate element having a first side including integrated circuitry thereon and having a back side;
providing at least one second semiconductor substrate element having a first side including a plurality of integrated circuitry thereon and having a backside;
stacking said first semiconductor element and said at least one second semiconductor substrate element in a superimposed relationship having the back side of the first semiconductor substrate element facing the back side of the at least one second semiconductor substrate element aligning vertically said first semiconductor substrate element and the at least one second semiconductor substrate element to vertically align integrated circuitry on said first semiconductor substrate element and at least one of the plurality of integrated circuits on said at least one semiconductor substrate element; and
severing from said stack traversely at least one dice pair comprising a die from said first semiconductor substrate element and an aligned second die from said at least one second semiconductor substrate element; and
adhesively attaching said first semiconductor substrate element and said at least one second semiconductor substrate element.
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Accused Products
Abstract
A method for increasing integrated circuit density comprising stacking an upper wafer and a lower wafer, each of which have fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complimentary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be diced into individual die pairs or wafer portions containing more than one die pair.
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Citations
24 Claims
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1. A method of fabricating a multi-level stack of semiconductor substrate elements, each of said elements including integrated circuitry, comprising:
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providing a first semiconductor substrate element having a first side including integrated circuitry thereon and having a back side;
providing at least one second semiconductor substrate element having a first side including a plurality of integrated circuitry thereon and having a backside;
stacking said first semiconductor element and said at least one second semiconductor substrate element in a superimposed relationship having the back side of the first semiconductor substrate element facing the back side of the at least one second semiconductor substrate element aligning vertically said first semiconductor substrate element and the at least one second semiconductor substrate element to vertically align integrated circuitry on said first semiconductor substrate element and at least one of the plurality of integrated circuits on said at least one semiconductor substrate element; and
severing from said stack traversely at least one dice pair comprising a die from said first semiconductor substrate element and an aligned second die from said at least one second semiconductor substrate element; and
adhesively attaching said first semiconductor substrate element and said at least one second semiconductor substrate element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24)
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12. A method of fabricating a multi-level stack of semiconductor wafer segments, each of said semiconductor wafer segments including integrated circuitry, comprising:
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providing a first semiconductor substrate segment having a first side including integrated circuitry thereon and having a back side;
providing at least one second semiconductor substrate segment having a first side including a plurality of integrated circuits thereon and having a backside;
stacking said first semiconductor substrate segment and said at least one second semiconductor substrate wafer in at least partially superimposed relationship to form a stack of semiconductor wafer segment;
separating said stack to form at least two semiconductor wafer segment stacks, each said semiconductor wafer segment stack comprising a first semiconductor wafer segment having a side including integrated circuitry and a back side and at least one second semiconductor wafer segment having a side including integrated circuitry and a back side, stacking said at least two semiconductor wafer segment stacks in at least partially superimposed relationship;
locating bond pads on said first semiconductor wafer segment of at least one of said at least two semiconductor wafer segment stacks on the side adjacent said at least one second semiconductor wafer segment of said at least one semiconductor wafer segment stack at a periphery thereof;
forming a notch through said at least one second semiconductor wafer segment of said at least one semiconductor wafer segment stack, said notch extending between and substantially perpendicular to a circuitry side and a back side of said at least one second semiconductor wafer segment to provide access to at least one said peripheral bond pad of said first semiconductor wafer segment of said at least one semiconductor wafer segment stack; and
adhesively attaching said first and said at least one second semiconductor wafer segments of said at least one semiconductor wafer segment stack.
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18. A method of fabricating a multi-level stack of semiconductor wafers, each of said semiconductor wafers including integrated circuitry, comprising:
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providing a first semiconductor wafer having a first side including integrated circuitry and having a back side;
providing at least one other semiconductor wafer having a first side including integrated circuitry and having a back side;
stacking said first semiconductor wafer and said at least one other semiconductor wafer in a superimposed relationship;
locating bond pads on said first semiconductor wafer of said stack on the side proximate said at least one other semiconductor wafer at a periphery thereof;
forming a notch through said at least one other semiconductor wafer, said notch substantially perpendicular to a circuitry side and a back side of said at least one other semiconductor wafer providing access to at least one said peripheral bond pads of said first semiconductor wafer of said stack; and
adhesively attaching said first semiconductor wafer and said at least one other semiconductor wafer.
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Specification