BIPOLAR TRANSISTOR STABILIZED WITH ELECTRICAL INSULATING ELEMENTS

• US 20020031892A1
• Filed: 12/03/1999
• Published: 03/14/2002
• Est. Priority Date: 05/30/1997
• Status: Active Grant

• Current Assignee: Achim Henkel, Patrice Salzenstein, Simone Cassette, Sylvain Delage
• Original Assignee: Achim Henkel, Patrice Salzenstein, Simone Cassette, Sylvain Delage
• Inventors: HENKEL, ACHIM, CASSETTE, SIMONE, DELAGE, SYLVAIN, SALZENSTEIN, PATRICE
• Granted Patent: US 6,451,659 B1
• Time in Patent Office: Days
• US Class Current: 438/312
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 29/0817 of heterojunction bipolar transistors H01L29/7375 takes precedence
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.

Claims

1. A heterojunction bipolar transistor based on III-V semiconductor materials comprising a collector, a base and an emitter and having a mesa located on the base, said transistor furthermore comprising electrically insulating elements in contact with the free surface of the base and in contact with the flanks of the mesa, the width of said elements being of the same magnitude as the width of said mesa.

2. A heterojunction bipolar transistor according to claim 1, wherein the width of each electrical insulating element is in the region of one micron, the width of the mesa being in the region of two microns.

3. A heterojunction bipolar transistor according to one of the claims 1 or 2, wherein the mesa is an emitter mesa constituted by n doped Ga_xIn_1-xP, the base is constituted by p doped Ga_yIn_1-yAs, the electrically insulating elements being formed by Ga_xIn_1-xP containing boron.

4. A heterojunction bipolar transistor according to one of the claims 1 to 3, wherein the mesa comprises, on the surface, an ohmic contact layer made of refractory metal of the TiWSi, WN, TiW or other type.

5. A heterojunction bipolar transistor according to one of the claims 1 to 4, further comprising a passivation layer covering the entire relief of the transistor.

6. A heterojunction bipolar transistor according to one of the claims 1 to 5 further comprising a heat sink in the form of a bridge lying on the one hand on the mesa and on the other hand on the substrate.

7. A method for making a heterojunction bipolar transistor based on III-V semiconductor materials comprising the epitaxial growth of semiconductor layers, a p type (or n type) doped layer of which, constituting the base, is contained between two n type (or p type) doped layers constituting the emitter and the collector, wherein said method further comprises:

the ion implantation, through a mask with a width l, of electrically insulating ions in the layer called the upper layer, located above the base layer;

the etching through a mask with a width L, greater than the width l, of the layer that has been made to be locally electrically insulating, so as to define electrically insulating elements on either side of doped semiconductor elements.

8. A method for the making of a bipolar transistor according to claim 7, wherein the layer called the upper layer and the base layer have different types of behavior with respect to ion implantation.

9. A method for the making of a bipolar transistor according to claim 8, wherein the layer located above the base layer is made of n doped Ga_xIn_1-xP and the base layer is constituted by p doped Ga_yIn_1-yAs.

10. A method for the making of a bipolar transistor according to any of the claims 7 to 9, wherein the mask with a width l is made of Ti/Au type metal.

11. A method for the making of a bipolar transistor according to any of the claims 7 to 9, wherein the mask with a width l is made of resin.