Method and system for testing RAMBUS memory modules
First Claim
1. An application specific integrated circuit for communicating test data between a test transaction engine and a RIMM associated with a RAMBUS Channel, comprising:
- a RAMBUS ASIC Channel cell for providing test data to a RAMBUS channel and accepting test data from the RAMBUS channel;
a channel controller interfaced with the RAMBUS ASIC Channel cell, the channel controller for controlling the writing and reading of test data by the RAMBUS ASIC Channel cell; and
at least one first-in-first-out circuit interfaced with the channel controller, the first-in-first-out circuit for accepting test data from the test transaction engine and providing test data to the test transaction engine.
6 Assignments
0 Petitions
Accused Products
Abstract
A system and method for testing a RIMM loaded with RDRAM integrated circuits generates and reads test transaction data with a test transaction engine, such as a microprocessor-based memory tester. A RIMM adapter interfaces with the test transaction engine and the RIMM under test to communicate test data, including test write, address, control and read data. A comparison of test read data returned to the test transaction engine from the RIMM against predetermined values allows a determination of the operational status of the RIMM. The RIMM adapter is embodied as an ASIC with plural FIFO circuits interfaced between the test transaction engine and a channel controller and RAC. The FIFOs reconcile differences in timing between generation and return of test data and demands by the RAC and channel controller. Separate read and write data paths between the test transaction engine and ASIC support improved rates of data transfer. The test transaction engine provides full speed test transactions by using instruction data to generate test data with FPGAs.
-
Citations
35 Claims
-
1. An application specific integrated circuit for communicating test data between a test transaction engine and a RIMM associated with a RAMBUS Channel, comprising:
-
a RAMBUS ASIC Channel cell for providing test data to a RAMBUS channel and accepting test data from the RAMBUS channel;
a channel controller interfaced with the RAMBUS ASIC Channel cell, the channel controller for controlling the writing and reading of test data by the RAMBUS ASIC Channel cell; and
at least one first-in-first-out circuit interfaced with the channel controller, the first-in-first-out circuit for accepting test data from the test transaction engine and providing test data to the test transaction engine. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A system for testing a RIMM, the system comprising:
-
a test transaction engine for generating and reading test transaction data to test the operation of the RIMM; and
A RIMM adapter interfaced with the test transaction engine, the RIMM adapter for communicating test transaction data between the test transaction engine and the RIMM. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 32, 33, 34, 35)
-
-
26. A method for testing a RIMM comprising the steps of:
-
generating test transaction information;
providing the test transaction information to the RIMM through a RIMM adapter for storage on the RIMM;
reading the stored test transaction information from the RIMM through the RIMM adapter; and
comparing the test transaction information read from the RIMM against predetermined results to determine the operational status of the RIMM.
-
Specification