Method and system of dynamic memory management

• US 20020032719A1
• Filed: 05/16/2001
• Published: 03/14/2002
• Est. Priority Date: 11/16/1998
• Status: Abandoned Application

• Current Assignee: RPX Corporation
• Original Assignee: Insignia Solutions Plc (America's Suppliers, Inc.)
• Inventors: Dias, Blaise Abel Alec, Guthrie, Philippa Joy, Rautenbach, Keith, Darnell, Stephen, Plummer, Wayne, Sexton, Jeremy James, Kramskoy, Jeremy Paul, Charnell, William Thomas, Wynn, Michael John, Thomas, Stephen Paul
• Application Number:
  US09/859,163
• Publication Number:
  US 20020032719A1
• Time in Patent Office: Days
• US Class Current: 718/107
• CPC Class Codes: G06F 11/3612 by runtime analysis performance monitoring G06F11/3466
• CPC Class Codes: G06F 12/0269 Incremental or concurrent garbage collection, e.g. in real-time systems G06F12/0261 takes precedence
• CPC Class Codes: G06F 2209/481 Exception handling
• CPC Class Codes: G06F 8/4442 Reducing the number of cache misses; Data prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 9/4484 Executing subprograms
• CPC Class Codes: G06F 9/449 Object-oriented method invocation or resolution
• CPC Class Codes: G06F 9/4491 Optimising based on receiver type
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06F 9/45516 Runtime code conversion or optimisation
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: Y10S 707/99932 Access augmentation or optimizing
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99956 File allocation

Abstract

A method and system of dynamic memory management. The method of managing memory in a computer system includes accessing the activation stack with a first thread, accessing the activation stack with a second thread, pausing the first thread only during a portion of time that the activation stack is accessed by the second thread, and managing access of the activation stack to prevent access of the activation stack by the first and second threads at the same time. The activation stack includes a plurality of frames, and a processor is utilized to activate and deactivate the threads.

Claims

1. A method of managing memory in a computer system, the computer system having an activation stack, the method comprising:

accessing the activation stack with a first thread;

accessing the activation stack with a second thread;

pausing the first thread only during a portion of time that the activation stack is accessed by the second thread; and

managing access of the activation stack to prevent access of the activation stack by the first and second threads at the same time.

2. A method as claimed in claim 1, wherein the activation stack includes a plurality of frames and the first and second threads access the activation stack one frame at a time, wherein access by the first thread of its current frame is paused only for the time it takes the second thread to access the current frame of the first thread.

3. A method as claimed in claim 1, further comprising providing a barrier to prevent return of the first thread from the current frame to a parent frame when the second thread is accessing the parent frame.

4. A method as claimed in claim 1, further comprising accessing the activation stack with a third thread.

5. A method as claimed in claim 4, further comprising providing a barrier to prevent return of the first thread from the current frame to a parent frame when the third thread is accessing the parent frame.

6. A method as claimed in claim 4, further comprising providing barriers associated with the second and third threads.

7. A method as claimed in claim 6, wherein each barrier includes a descriptor block and further comprising linking each of the descriptor blocks.

8. A method as claimed in claim 1, wherein the second thread is a garbage collector thread.

9. A computer system comprising:

an activation stack with a plurality of frames; and

a processor to activate and deactivate at least a first thread and a second thread, the first and second threads having access to the activation stack, the processor operable to pause the first thread during a portion of time that the activation stack is accessed by the second thread.

10. A system as claimed in claim 9, wherein the activation stack includes a plurality of frames and the first and second threads access the activation stack one frame at a time, wherein access by the first thread of its current frame is paused only for the time it takes the second thread to access the current frame of the first thread.

11. A system as claimed in claim 9, further comprising a first return barrier to prevent return of the first thread from the current frame to a parent frame when the second thread is accessing the parent frame.

12. A system as claimed in claim 9, wherein the processor is operable to activate and deactivate a third thread, the third thread having access to the activation stack.

13. A system as claimed in claim 12, further comprising a second return barrier to prevent return of the first thread from the current frame to a parent frame when the third thread is accessing the parent frame.

14. A system as claimed in claim 13, wherein each return barrier includes a descriptor block.

15. A system as claimed in claim 9, wherein the second thread is a garbage collector thread.

17. A method as claimed in claim 16, further comprising accessing the activation stack with a third thread.

19. A system as claimed in claim 18, wherein the activation stack includes a plurality of frames and the first and second threads access the activation stack one frame at a time, wherein access by the first thread of its current frame is paused only for the time it takes the second thread to access the current frame of the first thread.

20. A system as claimed in claim 19, further comprising a first return barrier to prevent return of the first thread from the current frame to a parent frame when the second thread is accessing the parent frame.

21. A system as claimed in claim 20, wherein the processor is operable to activate and deactivate a third thread, the third thread having access to the activation stack.

22. A system as claimed in claim 21, further comprising a second return barrier to prevent return of the first thread from the current frame to a parent frame when the third thread is accessing the parent frame.

23. A system as claimed in claim 22, wherein each return barrier includes a descriptor block.

24. A system as claimed in claim 18, wherein the second thread is a garbage collector thread.

16. A method of operating a computer system having an activation stack with a plurality of frames, each frame having data, and the frames organized according to age, each frame having a return address, the method comprising:

enabling a second thread to access a first thread in the stack;

suspending execution of the first thread only for the time it takes the second thread to examine the youngest frame in the activation stack;

editing the return address of a frame of interest to refer to a return barrier code;

allowing execution of the first thread to continue once a garbage collection thread has examined the youngest frame in the activation stack;

examining additional frames in the activation stack using the second thread; and

editing the return address of each frame examined by the second thread to refer to the return barrier code.

18. A computer system comprising:

a dynamic compiler, the dynamic compiler including;

an execution history recorder configured to record the number of times a fragment of code is executed, the execution history recorder having a threshold;

an interpreter coupled to the execution history recorder;

a compiler manager coupled to the execution history recorder;

a compiler coupled to the compiler manager, the compiler arranged to create compiled fragments of code having dominant code blocks and at least one outlier;

cache coupled to the dynamic compiler and managed by the compiler manager such that dominant code blocks are stored in one portion of the cache and the at least one outlier is stored in another portion of the cache;

an activation stack with a plurality of frames; and

a processor to activate and deactivate at least a first thread and a second thread, the first and second threads having access to the activation stack, the processor operable to pause the first thread during a portion of time that the activation stack is accessed by the second thread.