Semiconductor device

• US 20020033720A1
• Filed: 09/21/2001
• Published: 03/21/2002
• Est. Priority Date: 09/21/2000
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kanda, Kazushige, Ikehashi, Tamio
• Granted Patent: US 6,642,757 B2
• Time in Patent Office: Days
• US Class Current: 327/143
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

A semiconductor device includes an internal power supply terminal for supplying an internal power supply voltage, an oscillator generating a clock pulse when the internal power supply voltage becomes higher than a first voltage, a charge pump circuit charge pumping upon receiving the clock pulse, a reference voltage generator using the output voltage from the charge pump circuit as a power supply, and a voltage monitor which uses the output voltage from the charge pump circuit as a power supply, has a comparator for comparing a divided voltage of the internal power supply voltage with the reference voltage, and outputs a first signal of a first logic level as the power-on reset signal when the internal power supply voltage is higher than a second voltage. With this arrangement, a power-on reset circuit with little variation in power-on monitoring level can be provided.

Claims

1. A semiconductor device comprising:

an oscillator which starts generating a clock pulse when an externally supplied power supply voltage becomes higher than a first voltage;

a charge pump circuit configured to execute charge pumping operation upon receiving said clock pulse; and

a voltage monitor configured to generate a power-on reset signal upon receiving an output voltage from said charge pump circuit.

2. The device according to claim 1,

further comprising:

an internal power supply terminal configured to supply said power supply voltage as an internal power supply voltage, and

a reference voltage generator configured to generate a reference voltage using said output voltage from said charge pump circuit as a power supply, wherein

said voltage monitor uses said output voltage from said charge pump circuit as a power supply, has a comparator configured to compare a divided voltage of said internal power supply voltage with said reference voltage, and when said internal power supply voltage is higher than a second voltage, outputs a first signal of a first logic level as said power-on reset signal.

3. The device according to claim 1,

further comprising:

a voltage down converter configured to convert said power supply voltage into an internal power supply voltage, and

a reference voltage generator configured to generate a reference voltage using said output voltage from said charge pump circuit as a power supply, wherein

said voltage monitor uses said output voltage from said charge pump circuit as a power supply, has a comparator configured to compare a divided voltage of the internal power supply voltage with said reference voltage, and when said internal power supply voltage is higher than a second voltage, outputs a first signal of a first logic level as said power-on reset signal.

4. The device according to claim 1, wherein said charge pump circuit comprises a charge pump circuit section, a low-pass filter connected to an output side of said charge pump circuit section, and a capacitor configured to stabilize a charge-pumped voltage.

5. The device according to claim 1,

further comprising a logic circuit, wherein

said first voltage is a voltage at which said logic circuit starts operating.

6. The device according to claim 1, wherein said oscillator uses the power supply voltage as a power supply and is formed as a ring oscillator formed by connecting a substantially odd number of inverters in series.

7. The device according to claim 1, wherein oscillation operation of the oscillator is enabled upon receiving a signal representing that it is monitored that said power supply voltage becomes higher than said first voltage.

8. The device according to claim 1, further comprising a current source generator which uses said output voltage from said charge pump circuit as a power supply.

9. The device according to claim 1, further comprising a first charge-pumped voltage monitor configured to determine whether the output voltage from the charge pump circuit is higher or lower than a third voltage, and when said first charge-pumped voltage monitor determines that said output voltage from said charge pump circuit is lower than said third voltage, said first charge-pumped voltage monitor suppressing said first signal from changing to a first logic level independently of whether said internal power supply voltage is higher or lower than said second voltage.

10. The device according to claim 9, wherein said first charge-pumped voltage monitor suppresses said first signal from changing to said first logic level independently of whether said internal power supply voltage is higher or lower than said second voltage until an elapse of a first time that is required from a timing when said output voltage from said charge pump circuit becomes higher than said third voltage to a timing when said reference voltage generator and said voltage monitor are set in an operative state.

11. The device according to claim 1, further comprising a limiter configured to limit the output voltage from said charge pump circuit.

12. The device according to claim 11, wherein said limiter comprises diode-connected MOS transistors inserted between said output voltage from said charge pump circuit and said power supply voltage.

13. The device according to claim 11, wherein said limiter comprises diode-connected MOS transistors inserted between said output voltage from said charge pump circuit and a ground potential.

14. The device according to claim 11, wherein

said limiter comprises a second charge-pumped voltage monitor configured to compare a divided voltage of said output voltage from said charge pump circuit with said reference voltage and outputting a second signal, said second charge-pumped voltage monitor having a first monitoring level and a second monitoring level higher than said first monitoring level from when said divided voltage of said output voltage from said charge pump circuit becomes higher than said second monitoring level until said output voltage from said charge pump circuit drops and becomes lower than said first monitoring level, changing said second signal to said first logic level, and otherwise, keeping said second signal at a second logic level, and

when said second signal is at said first logic level, the oscillator forcibly stops generating said clock pulse.

15. The device according to claim 1, wherein when said first signal is at said first logic level, generation of said clock pulse by said oscillator is forcibly stopped, and terminals of an output of said charge pump circuit and said power supply voltage are short-circuited.

16. The device according to claim 15, further comprising a flag fixing circuit configured to execute control so that an output node of said charge pump circuit and said power supply voltage are short-circuited after a delay of a fixed time that is substantially equal to a time required until reference voltage generation operation by said reference voltage generator stabilizes since when a flag signal changes to said first logic level upon monitoring a rise of the internal power supply voltage by said voltage monitor.

17. The device according to claim 16, wherein said flag fixing circuit comprises a first NAND circuit whose one input terminal receives said flag signal, a second NAND circuit whose one input terminal receives an output from said first NAND circuit, a first inverter for receiving an output from said second NAND circuit, a delay circuit configured to delay a signal from said first inverter by a predetermined time, a third NAND circuit whose one input terminal receives an output from said delay circuit, whose other input terminal receives said output from said second NAND circuit, and whose output terminal is connected to the other input terminal of said second NAND circuit, a NOR circuit whose one input terminal receives said output from said delay circuit and whose other input terminal receives said output from said second NAND circuit, and a second inverter whose input terminal receives an output from said NOR circuit and whose output terminal is connected to the other input terminal of said first NAND circuit.

18. A semiconductor device comprising:

an internal power supply terminal configured to supply an externally supplied power supply voltage as an internal power supply voltage;

a reference voltage generator configured to generate a reference voltage from said internal power supply voltage;

a power-on reset circuit; and

a peripheral circuit other than said power-on reset circuit,

wherein after said reference voltage is generated, power-on reset operation of resetting said peripheral circuit other than said power-on reset circuit is executed.

19. A semiconductor device comprising:

a voltage down converter configured to generate a dropped voltage as an internal power supply voltage from an externally supplied power supply voltage;

a reference voltage generator configured to generate a reference voltage from said power supply voltage;

a power-on reset circuit; and

a peripheral circuit other than said power-on reset circuit,

wherein after said reference voltage is generated, power-on reset operation of resetting said peripheral circuit other than said power-on reset circuit is executed.

20. A semiconductor memory device comprising:

a memory cell array in which a plurality of memory cells are arranged;

a register configured to store data read out from said plurality of memory cells;

a reference voltage circuit configured to generate a reference voltage; and

a charge pump circuit configured to charge-pump a power supply voltage for said reference voltage circuit during a period of a read-out operation when said data are read out from said plurality of memory cells.

21. The device according to claim 20, wherein said charge pump circuit monitors a level of said power supply voltage during said read-out period when said data are read out from said memory cells and charge-pumps said power supply voltage for said reference voltage circuit in accordance with said monitored level of said power supply voltage.

22. The device according to claim 21, wherein said level of said power supply voltage to be monitored is a lower limit value of a readable power supply voltage.

23. The device according to claim 20, wherein fuse data is stored in a specific area of said memory cells.

24. The device according to claim 20, wherein said read-out operation is executed for a first time after the device is powered on.

25. The device according to claim 20, wherein said read-out operation is executed for a first time after said reference voltage is activated.

26. The device according to claim 20, wherein said read-out operation includes operation of reading out fuse data from said memory cells and storing the read-out fuse data in said register.

28. The device according to claim 27, wherein said predetermined potential is a lower limit value of a readable power supply voltage.

27. A semiconductor memory device comprising:

a memory cell array in which a plurality of memory cells are arranged;

a read-out circuit configured to read out data from the plurality of memory cells;

a reference voltage circuit configured to generate a reference voltage; and

a charge pump circuit, in a read-out operation in which a power supply voltage is not more than a predetermined potential, configured to supply a charge-pumped voltage higher than said power supply voltage not more than said predetermined potential as a power supply voltage for said reference voltage circuit.