Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby

• US 20020034844A1
• Filed: 11/30/2001
• Published: 03/21/2002
• Est. Priority Date: 06/04/1999
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Li-Kong Wang, Louis L. Hsu
• Inventors: Wang, Li-Kong, Hsu, Louis L.
• Granted Patent: US 6,649,959 B2
• Time in Patent Office: Days
• US Class Current: 438/164
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing
• CPC Class Codes: Y10S 438/948 Radiation resist

Abstract

A method of forming a semiconductor device, includes forming at least one conductive island having a predetermined sidewall angle in a conductive substrate, forming a dielectric material over the at least one island, forming a conductive material over the dielectric material, and forming a contact to the conductive material and the at least one island.

Claims

1. A method of forming a semiconductor device, comprising:

forming at least one conductive island having a predetermined sidewall angle in a conductive substrate;

forming a dielectric material over said at least one conductive island;

forming a conductive material over said dielectric material; and

forming a contact to said conductive material and said at least one conductive island.

2. The method according to claim 1, wherein said conductive substrate comprises a bulk silicon substrate.

3. The method according to claim 1, wherein said conductive substrate comprises a silicon-on-insulator (SOI) substrate.

4. The method according to claim 2, further comprising:

growing a field oxide on an exposed surface of said bulk silicon wafer; and

growing a node oxide over said at least one conductive island.

5. The method according to claim 1, further comprising:

wherein said conductive substrate comprises a bulk silicon substrate, said method further comprising;

forming a sidewall spacer on said at least one island.

6. The method according to claim 1, wherein said forming of said dielectric material comprises depositing said dielectric material.

7. The method according to claim 1, wherein said forming of said dielectric material comprises growing said dielectric material.

8. The method according to claim 1, wherein said dielectric material comprises a dielectric having a dielectric constant between about 4 and about 50.

9. The method according to claim 8, wherein said dielectric material comprises at least one of a ferroelectric film, Ta₂O₅, a nitride, and a composite dielectric material.

10. The method according to claim 1, further comprising:

patterning said conductive material formed over said dielectric material.

11. The method according to claim 10, further comprising:

patterning the conductive material located at a top portion of the conductive island.

12. The method according to claim 2, further comprising:

forming a sidewall spacer on said at least one island;

forming an oxide on an exposed surface of said bulk silicon wafer;

forming a node oxide over said at least one island; and

removing said sidewall spacer, prior to forming said dielectric material over said at least one conductive island.

13. The method according to claim 3, wherein said SOI wafer includes a silicon layer and an oxide layer, said method further comprising:

etching said silicon layer to reach the oxide layer, said oxide layer being a buried oxide layer.

14. The method according to claim 1, wherein said dielectric material includes at least one of thermal oxide and chemical vapor deposition nitride.

15. The method according to claim 1, wherein said conductive material includes at least one of doped polysilicon, aluminum, tungsten, and copper.

16. The method according to claim 3, wherein said SOI silicon thickness is greater than 3000 Å

.

17. The method according to claim 1, wherein a space of each said at least one island is made to have a sub-lithographic dimension such that a packing density of said semiconductor device is increased.

19. The method according to claim 18, wherein said spacing is formed smaller than a minimum lithographically patternable feature.

18. A method of forming a sub-lithographic pattern in a semiconductor device, comprising:

using a phase shift mask, forming a plurality of conductive islands having a predetermined sidewall angle in a conductive substrate;

forming a dielectric material over said islands;

forming a conductive material over said dielectric material; and

forming a contact to said conductive material and said islands, wherein a spacing size between adjacent islands is smaller than a width of an island.

20. A semiconductor device, comprising:

a conductive substrate;

at least one conductive island having a predetermined sidewall angle formed in said conductive substrate;

a dielectric material formed over said at least one island;

a conductive material formed over said dielectric material; and

a contact formed between said conductive material and said at least one island.

21. The semiconductor device according to claim 20, wherein a plurality of conductive islands are provided on said substrate, and

wherein a spacing between adjacent islands of said plurality of islands is smaller than a width of an island.

22. The device according to claim 20, wherein a plurality of conductive islands are provided on said substrate, and

wherein said spacing between adjacent islands is formed smaller than a minimum lithographically patternable feature.