Power consumption reduction in medical devices employing multiple supply voltages and clock frequency control

• US 20020035383A1
• Filed: 09/25/2001
• Published: 03/21/2002
• Est. Priority Date: 04/29/1998
• Status: Active Grant

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Thompson, David L.
• Granted Patent: US 6,434,425 B1
• Time in Patent Office: Days
• US Class Current: 607/16
• CPC Class Codes: A61N 1/3605 Implantable neurostimulators for stimulating central or peripheral nerve system
• CPC Class Codes: A61N 1/362 Heart stimulators heart defibrillators A61N1/39
• CPC Class Codes: A61N 1/372 Arrangements in connection with the implantation of stimulators
• CPC Class Codes: A61N 1/378 Electrical supply

Abstract

Power consumption in medical devices is reduced through the operation of circuits at clock speeds of lower levels to adequately complete desired functions during predetermined time periods (e.g., blanking interval, upper rate interval, etc.) just-in-time prior to subsequent required functional processes; by providing supply voltages tailored for various circuits of an integrated circuit; by operating two or more circuits of an integrated circuit at different clock frequencies; by changing the supply voltage level “on the fly” as required by specific circuit timing functions required for various circuitry based on clock frequencies used to control operation of such circuitry; and/or by tailoring back gate bias or adjusting back gate bias “on the fly” for circuits based on the supply voltage level applied to the circuits.

Claims

1. A medical device, comprising:

one or more circuits operable to perform at least one function during a predetermined time period, wherein the predetermined time period extends between a prior time period and a subsequent time period, and further wherein at least one of the circuits is operable for completing the at least one function in a predetermined number of clock cycles; and

a clock source for providing clock signals at a plurality of clock frequencies, the clock source operatively connected to control the at least one circuit at a clock frequency such that substantially the entire predetermined time period is used to perform the at least one function, wherein the function is completed just prior to the subsequent time period.

2. The device of claim 1. wherein the one or more circuits comprise at least a first logic circuit for performing a first function and a second logic circuit for performing a second function, wherein the first logic circuit is operable to perform the first function during a first predetermined time period and the second logic circuit is operable to perform the second function during a second predetermined time period, and further wherein each of the first and second logic circuits is operated at a different clock frequency such that substantially the entire respective first and second predetermined time periods are used by the respective first and second logic circuits to perform the respective first and second functions.

3. The device of claim 2, wherein the first predetermined time period and the second predetermined time period are time periods based on physiological events.

4. The device of claim 3, wherein at least one of the first and second time periods is a time period selected from the following group of time periods associated with cardiac events including blanking interval, upper rate interval, escape interval, refractory interval, and pulse generator/programmer handshake.

5. The device of claim 1, wherein the one or more circuits comprise a processing device, the processing device operable to perform a plurality of functions, each of the plurality of functions being performed during an associated predetermined time period prior to a subsequent time period in which another of the plurality of functions is performed, wherein the processing device is operable to perform each of two or more functions of the plurality of functions at a different clock frequency such that substantially the entire associated predetermined time period for each function is used to perform the functions prior to the subsequent time period in which another of the plurality of functions is performed.

6. The device of claim 5, wherein the associated predetermined time periods are time periods based on physiological events.

7. The device of claim 6, wherein at least one of the associated time periods are time periods selected from the following group of time periods associated with cardiac events including blanking interval, upper rate interval, escape interval, refractory interval, and pulse generator/ programmer handshake.

8. The device of claim 1, wherein the device further includes one or more supply voltage sources to provide one or more supply voltages, wherein the one or more supply voltage sources are operatively connected to the one or more circuits such that a supply voltage is applied to at least one circuit as a function of the clock frequency applied to the at least one circuit.

9. The device of claim 8, wherein the one or more circuits comprise at least a first logic circuit for performing a first function and a second logic circuit for performing a second function, wherein each of the first and second logic circuits is operated at a different clock frequency and further wherein each of the logic circuits has a different supply voltage applied thereto based on the different clock frequencies used to control the first and second logic circuits.

10. The device of claim 8, wherein the one or more circuits comprise a processing device, the processing device operable to perform a plurality of functions, wherein each of at least two of the plurality of functions is performed at a different clock frequency, and further wherein the supply voltage applied to the processing device is adjusted such that a first supply voltage is used for the processing device during performance of one of the at least two functions and a second supply voltage is used for the processing device during performance of the other function, wherein the first and second supply voltages are applied based on the different clock frequencies used to control the processing device.

11. The device of claim 1, wherein the one or more circuits are of a type selected from the group consisting of CMOS circuits. CML circuits, SOS circuits. SOI circuits, BICMOS circuits and NMOS circuits.

12. The device of claim 1, wherein the device is an hermetically sealed implantable medical device.

13. The device of claim 12, wherein the implantable medical device is selected from the group consisting of an implantable stimulator, an implantable nerve stimulator, an implantable pacemaker, an IPG, an implantable cardioverter, an implantable PCD, an implantable defibrillator, an implantable ICD and an implantable drug pump.

15. The device of claim 14, wherein the device further includes one or more clock circuits for providing clock signals at a plurality of clock frequencies, and further wherein the clock circuits are operatively connected to control each of two or more of the plurality of circuits at different clock frequencies.

16. The device of claim 15, wherein the at least one supply voltage of the plurality of different supply voltages operatively connected to the first circuit is applied based on the clock frequency used for controlling operation of the first circuit, and further wherein the at least one different supply voltage operatively connected to the second circuit is applied based on the clock frequency used for controlling operation of the second circuit.

17. The device of claim 15, wherein a particular circuit of the plurality of circuits performs at least a first and second function and wherein the one or more supply voltage sources operatively connected to the particular circuit includes:

a supply voltage source; and

a voltage regulator connected to the supply voltage source, wherein the voltage regulator adjusts the supply voltage source such that a first supply voltage applied to the particular circuit for performance of the first function is different than a second supply voltage applied to the particular circuit for performance of the second function.

18. The device of claim 17, wherein the first supply voltage and second supply voltage are determined based on the clock frequency used to control the particular circuit during the performance of the first function and the clock frequency used to control the particular circuit during the performance of the second function, respectively.

19. The device of claim 14, wherein the device further includes means for adjusting the back gate bias of at least one of the first and second circuits based on the supply voltage applied to the at least one circuit.

20. The device of claim 14, wherein the plurality of circuits are of at least one type selected from the group consisting of CMOS circuits, CML circuits, SOS circuits, SOI circuits, BICMOS circuits, PMOS circuits and NMOS circuits.

14. A medical device, comprising:

a plurality of circuits forming a single integrated circuit, wherein each circuit of the plurality of circuits is operable to perform at least one function; and

one or more supply voltage sources operable to provide a plurality of different supply voltages, wherein at least one supply voltage of the plurality of different supply voltages is operatively connected to at least a first circuit of the plurality of circuits, and further wherein at least one different supply voltage is operatively connected to at least a second circuit of the plurality of circuits.

21. A medical device, comprising:

processing circuitry for performing at least a first and second function;

a supply voltage source operatively connected to provide a supply voltage to the processing circuitry; and

a voltage regulator connected to the supply voltage source to adjust the supply voltage provided to the processing circuitry such that a first supply voltage level is applied to the processing circuitry during performance of the first function and a second supply voltage level is applied to the processing circuitry during performance of the second function, the second supply voltage level being different from the first supply voltage level.

22. The device of claim 21, wherein the device further includes an adjustable clock circuit for providing clock signals to control operation of the processing circuitry, and further wherein the clock circuit provides clock signals at a first frequency for control of the processing circuitry during performance of the first function and provides clock signals at a second frequency for control of the processing circuitry during performance of the second function.

23. The device of claim 22, wherein the first and second level of the supply voltage are applied based on the first and second frequency of the clock signals used for controlling operation of processing circuitry during performance of the first and second functions.

24. The device of claim 21, wherein the device further includes means for adjusting the back gate bias of the processing circuitry based on the first and second level of the supply voltage applied to the processing circuitry.

25. The device of claim 21, wherein the first function is performed at a frequency relatively higher than the frequency for performing the second function, and further wherein the second supply voltage level applied during the performance of the first function is high relative to the second supply voltage level.

26. The device of claim 25, wherein the first function is a function selected from the group of high speed telemetry uplink/downlink, morphology detection, device initialization, arrhythmia detection, far-field R-wave detection, EMI detection, and retrograde conduction.

27. The device of claim 25, wherein the second function is selected from the group of intrinsic heartbeat sensing, pacing, low speed telemetry, transtelephonic data transfer, remote data monitoring, and battery check.

28. The device of claim 21, wherein the device further includes:

a multiplexer for receiving a plurality of analog signals; and

an analog to digital converter for converting one or more of the analog signals to digital signals and applying such digital signals to the processing circuitry, wherein the processing circuitry operates on the digital signals representative of at least a first analog signal of the plurality of signals to perform the first function and operates on the digital signals representative of at least a second analog signal of the plurality of signals to perform the second function.

29. The device of claim 21, wherein the processing circuitry is of at least one type selected from the group consisting of CMOS circuitry, CML circuitry, SOS circuitry, SOI circuitry, BICMOS circuitry, PMOS circuitry and NMOS circuitry.

30. The device of claim 21, wherein the device is an hermetically sealed implantable medical device.

31. The device of claim 30. wherein the implantable medical device is selected from the group consisting of an implantable stimulator, an implantable nerve stimulator, an implantable pacemaker, an IPG, an implantable cardioverter, an implantable PCD, an implantable defibrillator, an implantable ICD and an implantable drug pump.

32. A method for conserving power for a medical device. the method comprising the steps of:

providing one or more circuits operable to perform at least one function during a predetermined time period that extends between a prior time period and a subsequent time period, wherein at least one of the circuits is operable for completing the at least one function in a predetermined number of clock cycles; and

operating the at least one circuit at a clock frequency such that substantially the entire predetermined time period is used to perform the at least one function, wherein the function is completed just prior to the subsequent time period.

33. The method of claim 32, wherein the one or more circuits comprise at, least a first logic circuit for performing a first function and a second logic circuit for performing a second function, and further wherein the operating step includes:

operating the first logic circuit to perform the first function during a first predetermined time period at a first clock frequency such that substantially the entire first predetermined time period is used by the first logic circuit to perform the first function; and

operating the second logic circuit at a second clock frequency that is different than the first clock frequency such that substantially the entire respective second predetermined time period is used by the second logic circuit to perform the second functions.

34. The method of claim 33, wherein at least one of the first predetermined time period and the second predetermined time period is a time period based on physiological events.

35. The method of claim 33, wherein the at least one of the first and second predetermined time periods are time periods selected from a group of time periods associated with cardiac events including blanking interval, upper rate interval, escape interval, refractory interval. and pulse generator/ programmer handshake.

36. The method of claim 32, wherein the one or more circuits comprise a processing device, the processing device operable to perform a plurality of functions, each of the plurality of functions being performed during an associated predetermined time period prior to a subsequent time period in which another of the plurality of functions is performed, and further wherein the operating step includes:

operating the processing device at a clock frequency to perform at least one function of the plurality of functions such that substantially the entire associated predetermined time period for the at least one function is used to complete the first function prior to a subsequent time period in which another of the plurality of functions is performed.

37. The method of claim 36, wherein the associated predetermined time period is a time period based on physiological events.

38. The method of claim 37, wherein the associated time period is a time period selected from a group of time periods associated with cardiac events including blanking interval, upper rate interval, escape interval, refractory interval, and pulse generator/programmer handshake.

39. The method of claim 32, wherein the method further includes controlling the level of a supply voltage applied to the at least one circuit as a function of the clock frequency.

40. The device of claim 32, wherein the step of providing one or more circuits further comprises the step of providing circuits of at least one type selected from the group consisting of CMOS circuits, CML circuits, SOS circuits, SOI circuits, BICMOS circuits, PMOS circuits and NMOS circuits.

41. The method of claim 32, further comprising the step of providing an hermetically sealed implantable medical device.

42. The method of claim 41, wherein the implantable medical device providing step further comprises the step of providing an implantable medical device selected from the group consisting of an implantable stimulator, an implantable nerve stimulator, an implantable pacemaker, an IPG, an implantable cardioverter, an implantable PCD, an implantable defibrillator, an implantable ICD and an implantable drug pump.

43. A method of conserving power in a medical device. the method comprising the steps of:

providing a plurality of circuits forming a single integrated circuit, wherein each circuit of the plurality of circuits is operable to perform at least one function; and

operating at least a first circuit of the plurality of circuits at a first supply voltage level; and

operating at least a second circuit of the plurality of circuits at a second supply voltage level, wherein the first supply voltage level is different than the second supply voltage level.

44. The method of claim 43, wherein the method further includes controlling each of the first and second circuits with a different clock frequencies.

45. The method of claim 44, wherein the controlling step further includes:

determining the first supply voltage level based on a clock frequency used for controlling operation of the first circuit; and

determining the second supply voltage level based on a clock frequency used for controlling operation of the second circuit.

46. The method of claim 45, wherein the method further includes adjusting the back gate bias of at least one of the first and second circuits based on the supply voltage level applied to the at least one circuit.

47. The device of claim 43, wherein the step of providing the plurality of circuits further comprises the step of providing circuits of at least one type selected from the group consisting of CMOS circuits, CML circuits, SOS circuits, SOI circuits, BICMOS circuits, PMOS circuits and NMOS circuits.

48. The method of claim 43, further comprising the step of providing an hermetically sealed implantable medical device.

49. The method of claim 48, wherein the implantable medical device providing step further comprises the step of providing an implantable medical device selected from the group consisting of an implantable stimulator, an implantable nerve stimulator, an implantable pacemaker, an IPG, an implantable cardioverter, an implantable PCD, an implantable defibrillator, an implantable ICD and an implantable drug pump.

50. A method of conserving power in a medical device, the method comprising the steps of:

providing processing circuitry operable for performing at least a first and second function;

operating the processing circuitry at a first supply voltage level to perform the first function; and

operating the processing circuitry at a second supply voltage level to perform the second function, wherein the first supply voltage level is different from the second supply voltage level.

51. The method of claim 50, wherein the method includes:

operating the processing circuitry at a first clock frequency to perform the first function; and

operating the processing circuitry at a second clock frequency to perform the second function, wherein the first clock frequency is different than the second clock frequency.

52. The method of claim 51, wherein the step of operating the processing circuitry at the first clock frequency and first supply voltage level and operating the processing circuitry at the second clock frequency and the second supply voltage level, include:

determining the first supply voltage level based on the first clock frequency; and

determining the second supply voltage level based on the second clock frequency.

53. The method of claim 50, wherein the method further includes adjusting the back gate bias of the processing circuitry based on the first and second supply voltage levels applied to the processing circuitry.

54. The method of claim 50, wherein method includes operating the processing circuitry to perform the first function at a clock frequency that is relatively higher than a clock frequency used to perform the second function.

55. The method of claim 54, wherein the first function is a function selected from the group of high speed telemetry uplink/downlink, morphology detection, device initialization, arrhythmia detection, far-field R-wave detection, EMI detection, and retrograde conduction.

56. The method of claim 54, wherein the second function is selected from the group of intrinsic heartbeat sensing, pacing, low speed telemetry, transtelephonic data, and battery check.

57. The device of claim 50, wherein the step of providing the processing circuitry further comprises the step of providing circuitry of at least one type selected from the group consisting of CMOS circuitry, CML circuitry, SOS circuitry, SOI circuitry. BICMOS circuitry. PMOS circuitry and NMOS circuitry.

58. The method of claim 50, further comprising the step of providing an hermetically sealed implantable medical device.

59. The method of claim 58, wherein the implantable medical device providing step further comprises the step of providing an implantable medical device selected from the group consisting of an implantable stimulator, an implantable nerve stimulator, an implantable pacemaker, an IPG, an implantable cardioverter, an implantable PCD, an implantable defibrillator. an implantable ICD and an implantable drug pump.