Image sensor with motion artifact supression and anti-blooming

• US 20020036300A1
• Filed: 10/26/2001
• Published: 03/28/2002
• Est. Priority Date: 01/06/1999
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Yang, Guang, Pain, Bedabrata, Yadid-Pecht, Orly, Wrigley, Chris
• Granted Patent: US 7,002,626 B2
• Time in Patent Office: Days
• US Class Current: 257/184
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14656 Overflow drain structures
• CPC Class Codes: H04N 25/531 by controlling rolling shutters in CMOS SSIS
• CPC Class Codes: H04N 25/623 by evacuation via the output or reset lines
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

An image sensor includes pixels formed on a semiconductor substrate. Each pixel includes a photoactive region in the semiconductor substrate, a sense node, and a power supply node. A first electrode is disposed near a surface of the semiconductor substrate. A bias signal on the first electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node. A second electrode is disposed near the surface of the semiconductor substrate. A bias signal on the second electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node. The image sensor includes a controller that causes bias signals to be provided to the electrodes so that photocharges generated in the photoactive region are accumulated in the photoactive region during a pixel integration period, the accumulated photocharges are transferred to the sense node during a charge transfer period, and photocharges generated in the photoactive region are transferred to the power supply node during a third period without passing through the sense node. The imager can operate at high shutter speeds with simultaneous integration of pixels in the array. High quality images can be produced free from motion artifacts. High quantum efficiency, good blooming control, low dark current, low noise and low image lag can be obtained.

Claims

1. A method of operating a photosensitive pixel, the method comprising:

biasing first and second transfer gates disposed in a vicinity of a photoactive region of a semiconductor substrate to accumulate photocharges in the photoactive region during a pixel integration period;

biasing the first and second transfer gates to transfer the accumulated photocharges to a sense node via a region of the semiconductor substrate disposed below the first transfer gate; and

subsequently biasing the first and second transfer gates to transfer additional photocharges in the photoactive region to a power supply node via a region of the semiconductor substrate disposed below the second transfer gate without passing the additional photocharges through the sense node.

2. The method of claim 1 wherein the second gate is biased to allow excess photocharges in the photoactive region to be transferred to the power supply node via the region of the semiconductor substrate below the second transfer gate during the integration period.

3. The method of claim 2 wherein during the pixel integration period the second transfer gate is biased with a voltage higher than a bias voltage on the first transfer gate.

4. The method of claim 1 including biasing a voltage on a photogate above the photoactive region to accumulate photocharges in the photoactive region during the pixel integration period.

5. The method of claim 4 including lowering a bias voltage on the photogate to transfer the accumulated photocharges to the sense node.

6. The method of claim 1 wherein biasing the first and second transfer gates to transfer the accumulated photocharges to a sense node in the pixel includes raising a bias voltage on the first transfer gate and lowering a bias voltage on the second transfer gate.

7. The method of claim 6 wherein biasing the first and second transfer gates to transfer additional photocharges in the photoactive region via the second transfer gate includes biasing the second transfer gate with a voltage higher than that of the first transfer gate.

8. The method of claim 7 wherein biasing the second transfer gate with a voltage higher than that of the first transfer gate includes raising the bias voltage applied to the second transfer gate and lowering the bias voltage applied to the first transfer gate.

9. A method of operating an image sensor having an array of photosensitive pixels, the method comprising:

accumulating photocharges in a respective photoactive region of a semiconductor substrate in each pixel of the array during a common pixel integration period;

biasing respective first and second transfer gates disposed in a vicinity of each photoactive region to transfer the accumulated photocharges from each photoactive region to respective sense nodes; and

subsequently biasing the respective first and second transfer gates to transfer additional photocharges in the photoactive regions to respective power supply nodes via respective regions of the semiconductor substrate below the second transfer gates, without passing the additional photocharges through the respective sense nodes.

10. The method of claim 9 including reading out signals stored by the respective sense nodes row by row, one row at a time.

11. The method of claim 10 wherein the reading out includes double sampling signals stored by the respective sense nodes.

12. The method of claim 9 wherein biasing the respective first and second transfer gates to transfer additional photocharges in the photoactive regions to respective power supply nodes is performed prior to commencing a subsequent pixel integration period.

14. The image sensor of claim 13 wherein the integration period of the pixels occurs at substantially the same time.

15. The image sensor of claim 13 wherein the controller provides a bias signal to the second electrode so that excess photocharges generated in the photoactive region are transferred to the power supply node during the pixel integration period.

16. The image sensor of claim 13 wherein the plurality of pixels include photogate-type pixels.

17. The image sensor of claim 13 wherein the plurality of pixels include photodiode-type pixels.

18. The image sensor of claim 13 wherein each pixel further includes a reset gate, wherein the controller provides a bias signal to the reset gate to cause charge in the pixel'"'"'s sense node to be transferred to a power supply node.

19. The image sensor of claim 13 the pixels are active pixels.

20. The image sensor of claim 13 wherein each pixel includes an amplifier and a pixel selection switch.

13. An image sensor comprising:

a plurality of pixels formed on a semiconductor substrate, wherein each pixel includes;

a photoactive region in the semiconductor substrate;

a sense node;

a first electrode disposed near a surface of the semiconductor substrate, wherein a bias signal on the first electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node;

a power supply node; and

a second electrode disposed near the surface of the semiconductor substrate, wherein a bias signal on the second electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node; and

a controller that causes bias signals to be provided to the electrodes so that photocharges generated in the photoactive region are accumulated in the photoactive region during a pixel integration period, the accumulated photocharges are transferred to the sense node during a charge transfer period, and additional photocharges generated in the photoactive region are transferred to the power supply node during a third period without passing through the sense node.

21. An image sensor comprising:

an array of pixels formed in a semiconductor substrate, wherein each pixel includes;

a photoactive region in the semiconductor substrate;

a sense node;

a power supply node; and

first and second transfer gates disposed in proximity to the surface of the semiconductor substrate; and

a controller that causes bias signals to be provided to the electrodes to operate the pixels in one of at least three modes including a first mode in which photocharges generated in the photoactive region of a pixel are accumulated in the pixel'"'"'s photoactive region, a second mode in which the accumulated photocharges are transferred to the pixel'"'"'s sense node via the pixel'"'"'s first transfer gate, and a third mode in which additional photocharges generated in the pixel'"'"'s photoactive region are transferred to the pixel'"'"'s power supply node via the pixel'"'"'s second transfer gate without passing through the pixel'"'"'s sense node.

22. The image sensor of claim 21 wherein each pixel is identified by a row and column in the array and includes a row selection switch that is selectively enabled by the controller to read out a signal stored by the pixel'"'"'s sense node.

23. The image sensor of claim 22 wherein the controller controls the row selection switches to read out the rows of pixels sequentially, one row of pixels at a time.

24. The image sensor of claim 21 in which each pixel is operated in the first mode at substantially the same time.

25. The image sensor of claim 24 in which each pixel is operated in the second mode at substantially the same time.