Method for fabricating semiconductor device capable of reducing parasitic capacitance and semiconductor device thereby

• US 20020036352A1
• Filed: 07/30/2001
• Published: 03/28/2002
• Est. Priority Date: 07/29/2000
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Sin, Hong-Jae, Kim, Jae-Hak, Han, Jae-Hyun
• Application Number:
  US09/919,340
• Publication Number:
  US 20020036352A1
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed is a semiconductor device capable of reducing parasitic capacitance and a method thereof, the method including the steps of depositing sequentially an inorganic silicon oxide layer and a low dielectric constant organic silicon oxide layer on a substrate, forming a partial trench with a predetermined depth in the organic silicon oxide layer by patterning, oxygenating an inner wall of the partial trench, and forming a trench by etching the partial trench with hydrofluoric acid (HF).

Claims

1. A method for fabricating a semiconductor device comprising the steps of:

sequentially depositing an inorganic silicon oxide layer on a substrate and an organic silicon oxide layer of a low dielectric constant on the inorganic silicon oxide layer;

forming a partial trench with a predetermined depth in the organic silicon oxide layer by patterning;

oxygenating an inner wall of the partial trench; and

forming a trench by etching the partial trench with hydrofluoric acid (HF).

2. The method of claim 1, the method further comprising the steps of:

depositing a conductive layer to fill the trench; and

removing a portion of the conductive layer stacked on a top surface of the organic silicon oxide layer by chemical-mechanical polishing (CMP).

3. The method of claim 1, the method further comprising the steps of:

forming a photo resist pattern exposing a predetermined portion of a bottom of the trench after the step of forming the trench; and

forming a contact hole by etching the inorganic silicon oxide layer with the photo resist pattern.

4. The method of claim 1, wherein the oxygenation is performed in an ashing step for the photo resist pattern formed during the patterning step.

5. The method of claim 1, wherein the oxygenation is performed at a region having a thickness less than 1000 Å

in an exposed region of the organic silicon oxide layer.

6. The method of claim 1, wherein the HF wet etching is performed in 5 seconds by a buffered oxide etchant (BOE).

7. A semiconductor device comprising:

a substrate having a conductive region formed thereon;

an inorganic silicon oxide layer formed on the substrate and convering at least a portion of a conductive region formed thereon;

an organic silicon oxide layer of a low dielectric constant formed on the inorganic silicon oxide layer;

a conductive interconnection formed with a predetermined line width in a depth of the same or more as a thickness of the organic silicon oxide layer; and

a contact plug penetrating the inorganic silicon oxide layer in a predetermined part for connecting electrically the conductive interconnection to the conductive region of the substrate.

8. The semiconductor device of claim 7, wherein the contact plug and the conductive interconnection are simultaneously formed in a manufacturing step.

9. The semiconductor device of claim 8, wherein the contact plug and the conductive interconnection are made of copper.

10. The semiconductor device of claim 7, wherein the organic silicon oxide layer is a silicon oxi-carbonate (SiOC) layer of silsesquioxane series containing carbon.

11. The semiconductor device of claim 10, wherein the organic silicon oxide layer is formed by chemical vapor deposition (CVD).