Semiconductor integrated circuit device having a hierarchical power source configuration

• US 20020036942A1
• Filed: 11/30/2001
• Published: 03/28/2002
• Est. Priority Date: 11/07/1994
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ooishi, Tsukasa
• Granted Patent: US 6,574,161 B2
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

A main source voltage transmission line for transmitting a source voltage VCH as one power source and a sub source voltage transmission line are provided corresponding to a gate circuit. A resistive element having a high resistance is provided between the main source voltage transmission line and the sub source voltage transmission line. A capacitor comprised of an insulated gate field effect transistor is connected to the sub source voltage transmission line. The gate circuit is operated with a voltage on the sub source voltage transmission line as an operating source voltage. Thus, the voltage on the sub source voltage transmission line can be maintained at a voltage level that balances with a sub-threshold current flowing through the gate circuit, and the voltage on the sub source line can be stably maintained by the capacitor. A semiconductor memory device can be realized which reduces the sub-threshold current that flows upon standby of the gate circuit and minimizes a difference in voltage between the sub source voltage transmission line and the main source voltage transmission line to operate at high speed with low current consumption.

Claims

1. A semiconductor integrated circuit device comprising:

a main voltage transmission line for transmitting a voltage of a first logic level;

a sub voltage transmission line;

a resistive element connected between said main voltage transmission line and said sub voltage transmission line;

a capacitor connected between said sub voltage transmission line and a node for supplying a voltage of a second logic level, said capacitor comprising an insulated gate type field effect transistor; and

a gate circuit operating with a voltage on said sub voltage transmission line as one operating source voltage, said gate circuit performing a predetermined logic process on a received signal and outputting a so-processed signal therefrom.

2. A semiconductor integrated circuit device comprising:

a main voltage transmission line for transmitting a voltage of a first logic level;

a plurality of sub voltage transmission lines;

a plurality of resistive elements respectively connected between respective ones of said plurality of sub voltage transmission lines and said main voltage transmission line; and

a plurality of gate circuits respectively divided into groups corresponding to said plurality of sub voltage transmission lines and operating with voltages on their corresponding sub voltage transmission lines as one operating source voltages, each said gate circuit performing a predetermined logic process on a received signal for outputting.

3. The semiconductor integrated circuit device as claimed in claim 2, further including a plurality of capacitors provided corresponding to said plurality of sub voltage transmission lines, each the capacitor having one electrode node connected to corresponding sub voltage transmission line and another electrode node supplied with a voltage of a second logic level, said plurality of capacitors each comprising an insulated gate type field effect transistor.

16. The semiconductor integrated circuit device as claimed in claim 2, further comprising:

means for interconnecting said plurality of sub voltage transmission lines for a predetermined period in response to a power-on detection signal.

17. The semiconductor integrated circuit device as claimed in claim 2, further comprising:

means for interconnecting each of said plurality of sub voltage transmission lines and said main voltage transmission line for a predetermined period in response to a power-on detection signal.

18. The semiconductor integrated circuit device as claimed in claim 2, further comprising:

means for interconnecting said plurality of sub voltage transmission lines for a predetermined period and connecting one of said plurality of sub voltage transmission lines to said main voltage transmission line in response to a power-on detection signal.

19. The semiconductor integrated circuit device as claimed in claim 2, further comprising:

a switching transistor provided between each of said plurality of sub voltage transmission lines and said main voltage transmission line and rendered conductive upon activation of either one of a power-on detection signal and a group specification signal for specifying a sub voltage transmission line.

20. The semiconductor integrated circuit device as claimed in any of claim 2, wherein said main voltage transmission line transmits a voltage higher than an operating power source voltage.

21. The semiconductor integrated circuit device as claimed in claim 20, further comprising:

a source voltage transmission line for transmitting the operating power source voltage; and

means provided between each of said plurality of sub voltage transmission lines and said source voltage transmission line, for connecting each of said sub voltage transmission lines and said source voltage transmission line together upon inactivation of a power-on detection signal.

22. The semiconductor integrated circuit device as claimed in claim 2, further comprising:

a plurality of switching transistors respectively provided corresponding to said plurality of sub voltage transmission lines and each switching transistor transmitting a voltage varying in a direction identical to that of a voltage on said main voltage transmission line at power-on of the device to a corresponding sub voltage transmission line for a predetermined period in response to a power-on detection signal.

24. The semiconductor integrated circuit device as claimed in claim 2, further comprising:

a memory array having a plurality of memory cells arranged in rows and columns;

a plurality of word lines disposed corresponding to the rows respectively and connected with memory cells on corresponding rows; and

a row decoder for decoding an applied address signal and generating a word line selection signal for selecting a word line addressed by the address signal in accordance with the result of decoding; and

wherein said plurality of gate circuits are word drivers provided corresponding to said plurality of word lines respectively, each for transmitting a voltage on a corresponding sub voltage transmission line to a corresponding word line when the word line selection signal outputted from said row decoder specifies the corresponding word line.

25. The semiconductor integrated circuit device as claimed in claim 24, wherein said plurality of word lines are further divided into a plurality of blocks and said word drivers are grouped into groups corresponding to said plurality of blocks of the word lines.

27. The semiconductor integrated circuit device as claimed in claim 26, wherein said plurality of word lines are further divided into a plurality of blocks and said word drivers are grouped into groups corresponding to said plurality of blocks of the word lines.

28. The semiconductor integrated circuit device as claimed claim 2, further comprising:

a memory array including a plurality of memory groups each having a plurality of memory cells arranged in rows and columns, said plurality of memory groups provided corresponding to said plurality of sub voltage transmission lines respectively;

a plurality of bit line pairs arranged corresponding to the respective columns and connected with the memory cells on corresponding columns;

a plurality of sense amplifiers each disposed between the adjacent memory groups and corresponding to each bit line pair in a corresponding memory group, said each for amplifying a difference in potential between the corresponding bit line pair; and

a plurality of connecting gates provided corresponding to the respective bit line pairs, for connecting corresponding bit line pair to corresponding sense amplifiers in response to a connection control signal; and

wherein each of said plurality of gate circuits is a connection control signal generating circuit for transmitting a voltage of a first logic level on the corresponding sub voltage transmission line to the corresponding connecting gate as the connection control signal.

29. The semiconductor integrated circuit device as claimed in claim 28, wherein said columns are further divided into a plurality of blocks and said connection control signal generating circuit is provided corresponding to each of said plurality of blocks of columns.

32. The semiconductor integrated circuit device as claimed claim 2, further comprising:

a memory array including a plurality of column groups each including a plurality of memory cells arranged in rows and columns, the column groups grouped in correspondence with groups of said sub voltage transmission lines respectively;

a plurality of bit line pairs arranged corresponding to the respective columns and connected with memory cells on corresponding columns; and

a plurality of equalize/precharge circuits disposed corresponding to the respective bit line pairs, and each the equalize/precharge circuit setting each bit line of a corresponding bit line pair to a predetermined voltage level in response to an equalize signal; and

wherein each of said plurality of gate circuits is an equalize signal generating circuit for transmitting a voltage of a first logic level on the corresponding sub voltage transmission line to equalize/precharge circuits in a corresponding group as an activated equalize signal.

33. The semiconductor integrated circuit device as claimed in claim 32, wherein said plurality of columns in each of said plurality of memory groups are further divided into a plurality of column blocks and said equalize signal generating circuit is disposed corresponding to each respective block of columns.

35. The semiconductor integrated circuit device as claimed in claim 34, wherein said plurality of columns in each of said plurality of memory groups are further divided into a plurality of column blocks and said equalize signal generating circuit is disposed corresponding to each respective block of columns.

36. The semiconductor integrated circuit device as claimed in claim 2, further comprising:

a memory-array including a plurality of column groups each including a plurality of memory cells arranged in rows and columns, the column groups grouped in correspondence with groups of said plurality of sub voltage transmission lines respectively;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cells on corresponding columns; and

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, and each the sense amplifier discharging a low-potential bit line of a corresponding bit line pair to a voltage of a second logic level upon activation thereof; and

wherein each of said gate circuits is a sense amplifier activating circuit for applying a voltage of a first logic level on a corresponding sub voltage transmission line to sense amplifiers in a corresponding column group as an activated signal upon activation thereof.

37. The semiconductor integrated circuit device as claimed in claim 36, wherein said plurality of columns in each of said plurality of column groups are further divided into a plurality of blocks and said sense amplifier activating circuit is disposed corresponding to each respective block of columns.

39. The semiconductor integrated circuit device as claimed in claim 38, wherein said plurality of columns in each of said plurality of column groups are further divided into a plurality of blocks and said sense amplifier activating circuit is disposed corresponding to each respective block of columns.

40. The semiconductor integrated circuit device as claimed in claim 2, further comprising:

a memory array including a plurality of groups each including a plurality of memory cells arranged in rows and columns and disposed in correspondence with each respective group of said plurality of sub voltage transmission lines;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cells on their corresponding columns; and

a plurality of sense amplifiers provided so as to corresponding to the respective bit line pairs, each sense amplifier setting a high-potential bit line of a corresponding bit line pair to a voltage of a first logic level upon activation thereof; and

wherein each of said gate circuits is a sense amplifier activation control circuit for transmitting a voltage of a first logic level on a corresponding sub voltage transmission line to sense amplifiers in a corresponding column group and maintaining the corresponding sense amplifiers at an inactive state upon a standby cycle.

41. The semiconductor integrated circuit device as claimed in claim 40, wherein said plurality of columns in each of said groups are further divided into a plurality of column blocks and said sense amplifier activation control circuit is disposed corresponding to each respective block of columns.

42. The semiconductor integrated circuit device as claimed in claim 2, further comprising:

a memory array including a plurality of groups each including a plurality of memory cells arranged in rows and columns and disposed in correspondence with each respective group of said plurality of sub voltage transmission lines;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cells on their corresponding columns; and

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, the sense amplifiers each setting a high potential bit line of a corresponding bit line pair to a voltage of a first logic level upon activation thereof; and

wherein each of said gate circuits is a sense amplifier activation control circuit for transmitting a voltage of the first logic level on a corresponding sub voltage transmission line to sense amplifiers in a corresponding column group and maintaining the corresponding sense amplifiers at an inactive state upon a standby cycle.

43. The semiconductor integrated circuit device as claimed in claim 42, wherein said plurality of columns in each of said groups are further divided into a plurality of column blocks and said sense amplifier activation control circuit is disposed corresponding to each respective block of columns.

44. The semiconductor integrated circuit device as claimed in claim 2, further comprising:

a memory cell array including a plurality of column groups each including a plurality of memory cells arranged in rows and columns, each column group provided in correspondence with said plurality of sub voltage transmission lines respectively;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cells on corresponding columns;

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, and each sense amplifier setting a high-potential bit line of a corresponding bit line pair to a voltage of a second logic level upon activation thereof; and

a plurality of sense amplifier activating transistors provided corresponding to the respective sense amplifiers, each transistor supplying a voltage of the second logic level to a corresponding sense amplifier to activate the corresponding sense amplifier upon conduction thereof; and

wherein each of said plurality of gate circuits is a sense control circuit for supplying a voltage of a first logic level on a corresponding sub voltage transmission line to sense amplifier activating transistors in a corresponding group upon activation thereof to bring the sense amplifier activating transistors into a conductive state.

45. The semiconductor integrated circuit device as claimed in claim 44, wherein the voltage of the first logic level is a negative voltage.

46. The semiconductor integrated circuit device as claimed in claim 44, wherein said plurality of columns in each of said column groups are further divided into a plurality of column blocks and said sense control circuit is disposed corresponding to each respective column block.

48. The semiconductor integrated circuit device as claimed in claim 47, wherein said plurality of columns in each of said groups are further divided into a plurality of column blocks and said sense amplifier activation control circuit is disposed corresponding to each respective block of columns.

49. The semiconductor integrated circuit device as claimed in claim 47, wherein the voltage of the first logic level is a negative voltage.

50. The semiconductor integrated circuit device as claimed in claim 47, wherein said plurality of columns in each of said column groups are further divided into a plurality of column blocks and said sense control circuit is disposed corresponding to each respective column block.

4. A semiconductor integrated circuit device comprising:

a first main voltage transmission line for transmitting a voltage of a first logic level;

a plurality of first sub voltage transmission lines;

a plurality of first resistive elements connected between respective ones of said plurality of first sub voltage transmission lines and said first main voltage transmission line;

a second main voltage transmission line for transmitting a voltage of a second logic level;

a plurality of second sub voltage transmission lines respectively disposed corresponding to said plurality of first sub voltage transmission lines;

a plurality of second resistive elements connected between respective ones of said plurality of second sub voltage transmission lines and said second main voltage transmission line; and

a plurality of gate circuits divided into a plurality of groups corresponding to respective pairs of said plurality of first sub voltage transmission lines and said plurality of second sub voltage transmission lines, each of the gate circuits operating with both voltages on corresponding first and second sub voltage transmission lines respectively as one operating source voltage and another operating source voltage, each the gate circuit performing a predetermined logic process on a received signal for outputting.

5. The semiconductor integrated circuit device as claimed in claim 4, further comprising:

a plurality of first capacitors respectively provided corresponding to said plurality of first sub voltage transmission lines, each the first capacitor having one electrode node connected to a corresponding first sub voltage transmission line and another electrode node supplied with a voltage of the second logic level, said plurality of first capacitors respectively comprising insulated gate type field effect transistors; and

a plurality of second capacitors respectively provided corresponding to said plurality of second sub voltage transmission lines, each the second capacitor having one electrode node connected to a corresponding second sub voltage transmission line and another electrode node supplied with a voltage of the first logic level, said plurality of second capacitors respectively comprising insulated gate type field effect transistors.

26. The semiconductor integrated circuit device as claimed in claim 4, further comprising:

a memory array having a plurality of memory cells arranged in rows and columns;

a plurality of word lines disposed corresponding to the rows respectively and connected with memory cells on corresponding rows; and

a row decoder for decoding an applied address signal and generating a word line selection signal for selecting a word line addressed by the address signal in accordance with the result of decoding; and

wherein said plurality of gate circuits are word drivers provided corresponding to said plurality of word lines respectively, each for transmitting a voltage on a corresponding sub voltage transmission line to a corresponding word line when the word line selection signal outputted from said row decoder specifies the corresponding word line.

30. The semiconductor integrated circuit device as claimed in claim 4, further comprising:

a memory array including a plurality of memory groups each having a plurality of memory cells arranged in rows and columns, said plurality of memory groups provided corresponding to said plurality of sub voltage transmission lines respectively;

a plurality of bit line pairs arranged corresponding the respective columns and connected with the memory cells on corresponding columns;

a plurality of sense amplifiers each disposed between the adjacent memory groups and corresponding to each bit line pair in a corresponding memory group, for amplifying a difference in potential between the corresponding bit line pair; and

a plurality of connecting gates provided for corresponding the respective bit line pairs, for connecting corresponding bit line pairs to corresponding sense amplifiers in response to a connection control signal and

wherein each of said plurality of gate circuits is a connection control signal generating circuit for transmitting a voltage of a first logic level on the corresponding sub voltage transmission line to the corresponding connecting gate as the connection control signal.

31. The semiconductor integrated circuit device as claimed in claim 30, wherein said columns are further divided into a plurality of blocks and said connection control signal generating circuit is provided corresponding to each of said plurality of blocks of columns.

34. The semiconductor integrated circuit device as claimed in claim 4, further comprising:

a memory array including a plurality of column groups each including a plurality of memory cells arranged in rows and columns, the column groups grouped in correspondence with groups of said sub voltage transmission lines respectively;

a plurality of bit line pairs arranged corresponding to the respective columns and connected with memory cells on corresponding columns; and

a plurality of equalize/precharge circuits disposed corresponding to the respective bit line pairs, each the equalize/precharge circuit setting each bit line of a corresponding bit line pair to a predetermined voltage level in response to an equalize signal; and

wherein each of said plurality of gate circuits is an equalize signal generating circuit for transmitting a voltage of a first logic level on the corresponding sub voltage transmission line to equalize/precharge circuits in a corresponding group as an activated equalize signal.

38. The semiconductor integrated circuit device as claimed in claim 4, further comprising;

a memory array including a plurality of column groups each including a plurality of memory cells arranged in rows and columns, the column groups grouped in correspondence with groups of said plurality of sub voltage transmission lines respectively;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cells on corresponding columns; and

a plurality of sense amplifiers corresponding the respective bit line pairs, the sense amplifier each discharging a low potential bit line of a corresponding bit line pair to a voltage of a second logic level upon activation thereof; and

wherein each of said gate circuits is a sense amplifier activating circuit for applying a voltage of a first logic level on a corresponding sub voltage transmission line to sense amplifiers in a corresponding column group as an activated signal upon activation thereof.

47. The semiconductor integrated circuit device as claimed in claim 4, further comprising:

a memory cell array including a plurality of column groups each including a plurality of memory cells arranged in rows and columns, each column group provided in correspondence with said plurality of sub voltage transmission lines respectively;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cells on corresponding columns;

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, sense amplifier each setting a high potential bit line of a corresponding bit line pair to a voltage of a second logic level upon activation thereof; and

a plurality of sense amplifier activating transistors provided corresponding to the respective sense amplifiers, each transistor supplying a voltage of the second logic level to a corresponding sense amplifier to activate the corresponding sense amplifier upon conduction thereof; and

wherein each of said plurality of gate circuits is a sense control circuit for supplying a voltage of a first logic level on a corresponding sub voltage transmission line to sense amplifier activating transistors in a corresponding group upon activation thereof to bring the sense amplifier activating transistors into a conductive state.

78. The semiconductor integrated circuit device as claimed i claim 4, further comprising:

a memory array including a plurality of column groups each including a plurality of memory cells arranged in rows and columns, the column groups grouped in correspondence with groups of said sub voltage transmission lines respectively;

a plurality of bit line pairs arranged corresponding to the respective columns and connected with memory cells on corresponding columns; and

a plurality of equalize/precharge circuits disposed corresponding to the respective bit line pairs, each the equalize/precharge circuit setting each bit line of a corresponding bit line pair to a predetermined voltage level in response to an equalize signal; and

wherein each of said plurality of gate circuits is an equalize signal generating circuit for transmitting a voltage of a first logic level on the corresponding sub voltage transmission line to equalize/precharge circuits in a corresponding group as an activated equalize signal.

6. A semiconductor integrated circuit device comprising:

a main voltage transmission node for supplying a voltage of a first logic level;

a sub voltage transmission node;

a voltage supply node for supplying a voltage of a second logic level;

a logic gate operating with a voltage on said sub voltage transmission node and a voltage on said voltage supply node both as operating source voltages to perform a predetermined logic process on a received signal for outputting; and

a variable resistance element connected between said sub voltage transmission node and said main voltage transmission node and coupled to have a resistance value thereof reduced in response to a signal outputted from said logic gate being at the first logic level.

7. The semiconductor integrated circuit device as claimed in claim 6, wherein said variable resistance element comprises a depletion type insulated gate field effect transistor.

8. The semiconductor integrated circuit device as claimed in claim 6, further comprising:

an insulated gate type field effect transistor having a threshold voltage and connected between said main voltage transmission node and said sub voltage transmission node, said insulated gate field effect transistor having a gate supplied with a voltage between the sum of a voltage on said main voltage transmission node and the threshold voltage, and the voltage on the said main voltage transmission node.

9. The semiconductor integrated circuit device as claimed in claim 6, further comprising:

a second main voltage transmission line for transmitting the voltage of the second logic level; and

a second variable resistance element provided between said second main voltage transmission line and said voltage supply node, said second variable resistance element being coupled to have a resistance value reduced in response to the output signal of said logic gate being at the second logic level.

10. The semiconductor integrated circuit device as claimed in claim 9, further comprising:

an insulated gate type field effect transistor having a threshold voltage and connected between said second main voltage transmission line and said voltage supply node, said insulated gate type field effect transistor having a gate supplied with a level of a voltage between the sum of a voltage on said second main voltage transmission line and the threshold voltage, and the voltage on said second main voltage transmission line.

11. The semiconductor integrated circuit device as claimed in claim 9, wherein said second variable resistance element comprises a depletion type insulated gate type field effect transistor.

13. The semiconductor integrated circuit device as claimed in claim 12, further comprising:

a second main voltage transmission node for supplying the voltage of the second logic level; and

a second insulated gate field effect transistor having one conduction electrode node connected to said voltage supply node, another conduction electrode node connected to said second main voltage transmission node and a gate electrode node connected to said voltage supply node, said second insulated gate field effect transistor causing a punchthrough phenomenon when the difference between the voltage on said voltage supply node and a voltage on said second main voltage transmission node reaches a predetermined value or greater.

15. The method as claimed in claim 14, further comprising the step of forming a spacer layer covering the first and second gate electrode layers prior to the ion implantation for forming the transistors.

64. The semiconductor integrated circuit device as claimed in claim 6, further comprising:

a memory array including a plurality of memory groups each having a plurality of memory cells arranged in rows and columns, said plurality of memory groups provided corresponding to said plurality of sub voltage transmission lines respectively;

a plurality of bit line pairs arranged corresponding to the respective columns and connected with the memory cells on corresponding columns;

a plurality of sense amplifiers each disposed between the adjacent memory groups and corresponding to each bit line pair in a corresponding memory group, for amplifying a difference in potential between the corresponding bit line pair; and

a plurality of connecting gates provided corresponding to the respective bit line pairs, for connecting corresponding bit line pair to corresponding sense amplifiers in response to a connection control signal; and

wherein each of said plurality of gate circuits is a connection control signal generating circuit for transmitting a voltage of a first logic level on the corresponding voltage transmission line to the corresponding connecting gate as the connection control signal.

65. The semiconductor integrated circuit device as claimed in claim 64, where in said columns are further divided into a plurality of blocks and said connection control signal generating circuit is provided corresponding to each of said plurality of blocks of columns.

66. The semiconductor integrated circuit device as claimed in claim 6, further comprising:

a memory array including a plurality of column groups each including a plurality of memory cells arranged in rows and columns, the column groups grouped in correspondence with groups of said sub voltage transmission lines respectively;

a plurality of bit line pairs arranged corresponding to the respective columns and connected with memory cells on corresponding columns; and

a plurality of equalize/precharge circuits disposed corresponding to the respective bit line pairs, each the equalize/precharge circuit setting each bit line of a corresponding bit line pair to a predetermined voltage level in response to an equalize signal; and

wherein each of said plurality of gate circuits is an equalize signal generating circuit for transmitting a voltage of a first logic level on the corresponding sub voltage transmission line to equalize/precharge circuits in a corresponding group as an activated equalize signal.

67. The semiconductor integrated circuit device as claimed in claim 67, wherein said plurality of columns in each of said plurality of memory groups are further divided into a plurality of column blocks and said equalize signal generating circuit is disposed corresponding to each respective block of columns.

68. The semiconductor integrated circuit device as claimed in claim 6, further comprising:

a memory array including a plurality of column groups each including a plurality of memory cells arranged in rows and columns, the column groups grouped in correspondence with groups of said plurality of sub voltage transmission lines respectively;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cells on corresponding columns; and

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each the sense amplifier discharging a low-potential bit line of a corresponding bit line pair to a voltage of a second logic level upon activation thereof; and

wherein each of said gate circuits is a sense amplifier activating circuit for applying a voltage of a sense amplifiers in a corresponding column group as an activated signal upon activation thereof.

69. The semiconductor integrated circuit device as claimed in claim 68, wherein said plurality of columns in each of said plurality of column groups are further divided into a plurality of blocks and said sense amplifier activating circuit is disposed corresponding to each respective block of columns.

70. The semiconductor integrated circuit device as claimed in claim 6, further comprising:

a memory array including a plurality of groups each including a plurality of memory cells arranged in rows and columns and disposed in correspondence with each respective group of said plurality of sub voltage transmission lines;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cells on their corresponding columns; and

a plurality of sense amplifier provided corresponding to the respective bit line pairs, each sense amplifier setting a high-potential bit line of a corresponding bit line pair to a voltage of a first logic level upon activation thereof; and

wherein each of said gate circuits is a sense amplifier activation control circuit for transmitting a voltage of a first logic level on a corresponding sub voltage transmission line to a sense amplifiers in a corresponding column group and maintaining the corresponding sense amplifiers at an inactive state upon a standby cycle.

71. The semiconductor integrated circuit device as claimed in claim 70, wherein said plurality of columns in each of said groups are further divided into a plurality of column blocks and said sense amplifier activation control circuit is disposed corresponding to each respective block of columns.

72. The semiconductor integrated circuit device as claimed in claim 6, further comprising:

a memory cell array including a plurality of column groups each including a plurality of memory cells arranged in rows and columns, each column group provided in correspondence with said plurality of sub voltage transmission lines respectively;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cells on corresponding columns;

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each sense amplifier setting a high-potential bit line of a corresponding bit line pair to a voltage of a second logic level upon activation thereof; and

a plurality of sense amplifier activating transistors provided corresponding to the respective sense amplifiers, each transistor supplying a voltage of the second logic level to a corresponding sense amplifier to activate the corresponding sense amplifier upon conduction thereof; and

wherein each of said plurality of gate circuits is a sense control circuit for supplying a voltage of a first logic levels on a corresponding sub voltage transmission line to sense amplifier activating transistors in a corresponding group upon activation thereof to bring the sense amplifier activating transistors into a conductive state.

73. The semiconductor integrated circuit device as claimed in claim 72, wherein said plurality of columns in each of said groups are further divided into a plurality of column blocks and said sense amplifier activation control circuit is disposed corresponding to each respective block of columns.

74. The semiconductor integrated circuit device as claimed in claim 72, wherein the voltage of the first logic level is a negative voltage.

75. The semiconductor integrated circuit device as claimed in claim 72, wherein said plurality of columns in each of said column groups are further divided into a plurality of column blocks and said sense control circuit is disposed corresponding to each respective column block.

76. The semiconductor integrated circuit device as claimed in claim 12, further comprising:

a memory array including a plurality of memory groups each having a plurality of memory cells arranged in rows and columns, said plurality of memory groups provided corresponding to said plurality of sub voltage transmission lines respectively;

a plurality of bit line pairs arranged corresponding to the respective columns and connected with the memory cells on corresponding columns;

a plurality of sense amplifiers each disposed between the adjacent memory groups and corresponding to each bit line pair in a corresponding memory group, amplifying a difference in potential between the corresponding bit line pair; and

a plurality of connecting gates provided corresponding to the respective bit line pairs for connecting corresponding bit line pair to corresponding sense amplifiers in response to a connection control signal; and

wherein each of said plurality of gate circuits is a connection control signal generating circuit for transmitting a voltage of a first logic level on the corresponding sub voltage transmission line to the corresponding connecting gate as the connection control signal.

77. The semiconductor integrated circuit device as claimed in claim 76, wherein said columns are further divided into a plurality of blocks and said connection control signal generating circuit is provided corresponding to each of said plurality of blocks of columns.

79. The semiconductor integrated circuit device as claimed in claim 78, wherein said plurality of columns in each of said plurality of memory groups are further divided into a plurality of column blocks and said equalize signal generating circuit is disposed corresponding to each respective block of columns.

80. The semiconductor integrated circuit device as claimed in claim 12, further comprising:

a memory array including a plurality of column groups, each including a plurality of memory cells arranged in rows and columns, the column groups in correspondence with groups of said plurality of sub voltage transmission lines respectively;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cells on corresponding columns; and

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each the sense amplifier discharging a low-potential bit line of a corresponding bit line pair to a voltage of a second logic level upon activation thereof; and

wherein each of said gate circuits is a sense amplifier activating circuit for applying a voltage of a first logic level on a corresponding sub voltage transmission line to sense amplifiers in a corresponding column group as an activated signal upon activation thereof.

81. The semiconductor integrated circuit device as claimed in claim 80, wherein said plurality of columns in each of said plurality of column groups are further divided into a plurality of blocks and said sense amplifier activating circuit is disposed corresponding to each respective block of columns.

82. The semiconductor integrated circuit device as claimed in claim 12, further comprising:

a memory array including a plurality of groups each including plurality of memory cells arranged in rows and columns and disposed in correspondence with each respective group of said plurality of sub voltage transmission lines;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cells on their corresponding columns; and

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each sense amplifier setting a high-potential bit line of a corresponding bit line pair to a voltage of a first logic level upon activation thereof; and

wherein each of said gate circuits is a sense amplifier activation control circuit for transmitting a voltage of a first logic level on a corresponding sub voltage transmission line to sense amplifier in a corresponding column group and maintaining the corresponding sense amplifiers at an inactive state upon a standby cycle.

83. The semiconductor integrated circuit device as claimed in claim 82, wherein said plurality of columns in each of said groups are further divided into a plurality of column blocks and said sense amplifier activation control circuit is disposed corresponding to each respective block of columns.

84. The semiconductor integrated circuit device as claimed in claim 12, further comprising:

a memory cell array including a plurality of column groups each including a plurality of memory cells arranged in rows and columns, each column group provided in correspondence with said plurality of sub voltage transmission lines respectively;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cells on corresponding columns;

a plurality of sense amplifiers provided corresponding to the respective bit line of a corresponding bit line pair to a voltage of a second logic level upon activation thereof; and

a plurality of sense amplifier activating transistors provided corresponding to the respective sense amplifiers, each transistor supplying a voltage of the second logic level to a corresponding sense amplifier to activate the corresponding sense amplifier upon conduction thereof; and

wherein each of said plurality of gate circuits is a sense control circuit for supplying a voltage of a first each respective group of said plurality of sub voltage transmission lines;

a plurality of bit line pairs disposed corresponding to the respective columns and connected with memory cell on their corresponding columns; and

a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each sense amplifier setting a high-potential bit line of a corresponding bit line pair to a voltage of a first logic level upon activation thereof; and

wherein each of said gate circuits is a sense amplifier activation control circuit for transmitting a voltage of a first logic level on a corresponding sub voltage transmission line to sense amplifier activating transistors in a corresponding column group upon activation thereof to bring the sense amplifier activating transistors into a conductive state.

85. The semiconductor integrated circuit device as claimed in claim 84, wherein said plurality of columns in each of said groups are further divided into a plurality of column blocks and said sense amplifier activation control circuit is disposed corresponding to each respective block of columns.

86. The semiconductor integrated circuit device as claimed in claim 84, wherein the voltage of the first logic level is a negative voltage.

87. The semiconductor integrated circuit device as claimed in claim 84, wherein said plurality of columns in each of said column groups are further divided into a plurality of column blocks and said sense control circuit is disposed corresponding to each respective column block.

12. A semiconductor integrated circuit device comprising:

a main voltage transmission node for supplying a voltage of a first logic level;

a sub voltage transmission node;

a voltage supply node for supplying a voltage of a second logic level;

a logic gate operating with a voltage on said sub voltage transmission node and a voltage on said voltage supply node both as operating source voltages to perform a predetermined logic process on a received signal for outputting; and

an insulated gate type field effect transistor connected between said main voltage transmission node and said sub voltage transmission node, and having a gate connected to said sub voltage transmission node, said insulated gate type field effect transistor causing a punchthrough phenomenon when the difference between a voltage on said main voltage transmission node and the voltage on said sub voltage transmission node reaches a predetermined value or greater.

14. A method of manufacturing a semiconductor integrated circuit device, comprising the steps:

simultaneously forming first and second gate electrode layers on a first conductivity type semiconductor substrate region, said first and second gate electrode layers being separated from each other;

implanting ions into the substrate region to form impurity regions in self-alignment with the first and second gate electrode layers and forming first and second insulated gate type field effect transistors between which an impurity region formed in the substrate region between the first and second gate electrode layers is shared;

covering a region for forming the first insulated gate type field effect transistor with a mask layer;

obliquely implanting ions into a region of the second insulated gate field effect transistor in self-alignment with the second gate electrode layer to reduce a distance between impurity regions of the second insulated gate field effect transistor; and

connecting the first gate type electrode layer and a signal input node with one another, connecting the second gate electrode layer of the second insulated gate type field effect transistor and the impurity region formed between the first and second gate electrode layers with one another and connecting the remaining impurity region of the second insulated gate field effect transistor and a node for supplying a voltage of a first logic level to each other.

23. A semiconductor integrated circuit device comprising:

a main voltage transmission line for transmitting a voltage of a first logic level;

a plurality of sub voltage transmission lines;

a plurality of gate circuits grouped corresponding to said plurality of sub voltage transmission lines respectively, each the gate circuit performing a predetermined process on a received signal for outputting;

a plurality of first switching transistors provided corresponding to said plurality of sub voltage transmission lines respectively, each the first switching transistor connecting a corresponding sub voltage transmission line to said main voltage transmission line in response to a group specification signal for specifying a sub voltage transmission line; and

a plurality of second switching transistors provided corresponding to said plurality of sub voltage transmission lines respectively, each the second switching transistor transmitting a voltage closer to a voltage of a second logic level than to the voltage of the first logic level to a corresponding sub voltage transmission line upon non designation by the group specification signal.

51. A semiconductor integrated circuit device comprising:

a memory-array having a plurality of memory cells arranged in rows and columns;

a plurality of word lines disposed corresponding to said rows respectively and connected with memory cells on corresponding rows;

a plurality of decoders each provided corresponding to two word lines, each the decoder decoding a first address signal inputted thereto and outputting a decode signal indicative of the result of decoding therefrom;

a plurality of first word drivers provided corresponding to said plurality of decoders respectively, each the first word driver transmitting a high voltage to a first word line of corresponding two word lines in accordance with a decode signal outputted from a corresponding decoder and a second address signal;

a global high voltage supply line for supplying a high voltage greater than an operating source voltage;

a first sub high voltage transmission line supplied with the high voltage from said global high voltage supply line, for supplying the high voltage to each of said plurality of first word drivers;

a first switching transistor connected between said global high voltage supply line and said first sub high voltage transmission line to conduct in response to a first control signal;

a plurality of second word drivers disposed corresponding to said plurality of decoders respectively and arranged in line with corresponding decoders and corresponding first word drivers along a row direction, each the second word driver transmitting the high voltage to a second word line of the corresponding two word lines in response to the signal outputted from the corresponding decoder and a signal complementary to the second address signal;

a second sub high voltage transmission line supplied with the high voltage from said global high voltage supply line, for supplying the high voltage to said plurality of second word drivers; and

a second switching transistor connected between said global high voltage supply line and said second sub high voltage transmission line to conduct in response to a second control signal.

57. The semiconductor integrated circuit device as claimed in claim 51, wherein either one of the first and second control signals is brought into an active state in response to the second address signal to bring either one of said first and second switching transistors into a conducting state.

58. The semiconductor integrated circuit device as claimed in claim 51, wherein either one of the first and second control signals is brought into an active state in response to the second address signal to bring either one of said first and second switching transistors into a conducting state.

52. A semiconductor integrated circuit device comprising:

a memory array having a plurality of memory cells arranged in rows and columns;

a plurality of word lines disposed so as to corresponding to the rows respectively and connected with the memory cells on corresponding rows;

a plurality of decoders disposed corresponding to respective pairs of two word lines, each the decoder decoding a first address signal specifying a word line pair and outputting a decode signal indicative of the result of decoding therefrom;

a global high voltage supply line for transmitting a high voltage generated from a high voltage generating circuit;

first and second main high voltage transmission lines coupled to said global high voltage supply line;

first and second sub high voltage transmission lines each supplied with the high voltage from said global high voltage supply line, said first and second sub high voltage transmission lines transmitting the supplied high voltage and disposed in parallel to and away from said first and second main high voltage transmission lines;

first and second switching transistors respectively connected between said global high voltage supply line and said first sub high voltage transmission line and between said global high voltage supply line and said second sub high voltage transmission line, for connecting said global high voltage supply line and a corresponding sub high voltage transmission line to each other upon conduction thereof; and

regions for forming first and second word drivers provided corresponding to said plurality of decoders respectively and disposed in line along a row extending direction.

53. The semiconductor integrated circuit device as claimed in claim 52, wherein said region comprises;

a first word driver forming region comprising;

a first transistor forming region for forming a first first conductivity type insulated gate field effect transistor for precharging a first internal node to a voltage level on said first main high voltage transmission line response to a precharge signal, a second first conductivity type insulated gate field effect transistor for charging the first internal node to the voltage level on said first main high voltage transmission line in response to a potential on the first word line of a corresponding word line pair, and a third first conductivity type insulated gate field effect transistor for transmitting a voltage on said first sub high voltage transmission line to the first word line in response to a voltage on the first internal node; and

a second transistor forming region for forming a second conductivity type insulated gate field effect transistor transmitting a signal outputted from a corresponding decoder to the first internal node in response to a second address signal specifying one of the first and second word lines of each respective word line pair; and

a second word driver forming region comprising;

a third transistor forming region for forming a fourth first conduction-type insulated gate field effect transistor for precharging a second internal node to a voltage level on said second main high voltage transmission line in response to the precharge signal, a fifth first conductivity type insulated gate field effect transistor for charging the second internal node to the voltage level on said second main high voltage transmission line in response to a potential on the second word line of the corresponding word line pair, a sixth first conductivity type insulated gate field effect transistor for transmitting a voltage on said second sub high voltage transmission line to the second word line in response to a voltage on the second internal node; and

a fourth transistor forming region for forming a second second conductivity type insulated gate field effect transistor for transmitting the signal outputted from a corresponding row decoder to the second internal node in response to a complement of the second address signal.

54. The semiconductor integrated circuit device as claimed in claim 53, wherein said second transistor forming region includes a third second conductivity type insulated gate field effect transistor for discharging the corresponding first word line to a ground potential level in response to the potential on the first internal node and said fourth transistor forming region includes a fourth second conductivity type insulated gate field effect transistor for charging the corresponding second word line to a ground potential level in response to the potential on the second internal node.

55. The semiconductor integrated circuit device as claimed in claim 54, wherein said first, second, fourth and third transistor forming regions are arranged extending in a named order from the corresponding decoder to the corresponding word line pair.

56. The semiconductor integrated circuit device as claimed in claim 55, wherein transistors in said first and second transistor forming regions are placed symmetrically to transistors in said third and fourth transistor forming regions with respect to a region formed between said second transistor forming region and said fourth transistor forming region.

59. The semiconductor integrated circuit device as claimed in claim 52, wherein said first and second main high voltage transmission line are arranged extending over the first and third transistor forming regions in a direction normal to the row extending direction.

60. The semiconductor integrated circuit device as claimed in claim 52, wherein said first main high voltage transmission line is arranged extending over the first and second insulated gate type field effect transistors in a direction normal to the row extending direction.

61. The semiconductor integrated circuit device as claimed in claim 52, wherein the second main high voltage transmission line is arranged extending over the fourth and fifth insulated gate type field effect transistor in a direction normal to the row extending direction.

62. The semiconductor integrated circuit device as claimed in claim 52, wherein a line width of each of the first and second main high voltage transmission lines is smaller than that of each of the first and second sub high voltage transmission lines.

63. An internal voltage generating circuit comprising:

a first capacitor having one electrode node supplied with a first clock signal having a predetermined amplitude and another electrode node connected to an internal node;

an insulated gate field effect transistor having one conduction electrode node connected to the internal node, another conduction electrode node connected to an output node and a gate electrode node;

a first precharge element for precharging the internal node to a predetermined voltage level corresponding-to a first logic level;

a second precharge element for precharging the gate electrode node of said insulated gate field effect transistor to the predetermined voltage level corresponding to the first logic level;

a drive element for outputting a signal at a voltage level on the output node in response to a second clock signal different in phase from the first clock signal being at a second logic level; and

a second capacitor having one electrode node connected to an output of said drive element and another electrode node connected to the gate electrode node of said insulated gate field effect transistor;

said insulated gate field effect transistor being brought into a conductive state when said drive element outputs the signal having the voltage level on the output node.