METHOD AND APPARATUS FOR IMPLEMENTING MULTIPLE MEMORY BUSES ON A MEMORY MODULE

• US 20020038405A1
• Filed: 09/30/1998
• Published: 03/28/2002
• Est. Priority Date: 09/30/1998
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: LEDDIGE, MICHAEL W., HORINE, BRYCE D., MACWILLIAMS, PETER D., BONELLA, RANDY
• Granted Patent: US 6,587,912 B2
• Time in Patent Office: Days
• US Class Current: 711/115
• CPC Class Codes: G06F 13/4256 using a clocked protocol

Abstract

A memory module includes a first memory bus. A memory repeater hub is coupled to the first memory bus. A second memory bus is coupled in series with the memory repeater hub.

Claims

1. A memory module, comprising:

a first memory bus;

a memory repeater hub coupled to the first memory bus; and

a second memory bus coupled in series with the memory repeater hub.

2. The memory module of claim 1, further comprising a third memory bus coupled in series with the memory repeater hub in parallel with the second memory bus.

3. The memory module of claim 1, further comprising a plurality of memory devices coupled to the second memory bus.

4. The memory module of claim 1, further comprising a plurality of memory devices coupled to the third memory bus.

5. The memory module of claim 1, wherein the first memory bus is routed from the memory repeater hub to an electrical connector that routes the first memory bus off the memory module.

6. The memory module of claim 1, wherein the memory repeater hub routes signals to one of the second memory bus and the third memory bus in response to address information received from the first memory bus.

7. A computer system, comprising:

a bus;

a processor coupled to the bus;

a memory controller coupled to the bus;

a first memory bus;

a memory system, that includes a first memory module coupled to the memory controller via the first memory bus, the first memory module having a second memory bus connected in series with the first memory bus via a memory repeater hub.

8. The computer system of claim 7, further comprising a third memory bus coupled in series with the memory repeater hub and in parallel with the second memory bus.

9. The computer system of claim 7, further comprising a plurality of memory devices on the first memory module coupled to the second memory bus.

10. The computer system of claim 7, further comprising a plurality of memory devices on the first memory module coupled to the third memory bus.

11. The computer system of claim 7, wherein the first memory bus is routed from the memory repeater hub to an electrical connector that routes the first memory bus off the memory module.

12. The computer system of claim 11, further comprising a second memory module coupled to the first memory bus.

13. The computer system of claim 12, wherein the second memory module further comprises a third memory bus connected in series with the first memory bus via a second memory repeater hub.

14. The computer system of claim 13, further comprising a plurality of memory devices on the second memory module coupled to the third memory bus.

15. The computer system of claim 12, further comprising a plurality of memory devices on the second memory module coupled to the first memory bus.

17. The method of claim 16, wherein determining whether the signals addressed to a memory device is on the memory module, comprises:

reading a first portion of address information to identify the identity of the memory device;

reading a second portion of the address information to identify the identity of a memory bus that the memory device is connected to; and

comparing the identity of the memory device and the identity of the memory bus to memory module information.

16. A method for routing signals on a memory module, comprising:

determining whether signals addressed to a memory device is on the memory module;

routing the signals to a first memory bus on the memory module connected to the memory device if the memory device is on the memory module; and

routing the signals to a second memory bus on the memory module that is connected to a second memory module if the memory device is not on the memory module.