Nonvolatile memory structures and fabrication methods

• US 20020038897A1
• Filed: 10/09/2001
• Published: 04/04/2002
• Est. Priority Date: 08/15/2000
• Status: Active Grant

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: ProMOS Technologies, Inc.
• Inventors: Tuan, Hsing Ti, Li, Li-Chun
• Granted Patent: US 6,643,186 B2
• Time in Patent Office: Days
• US Class Current: 257/372
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Claims

1. A method for manufacturing an integrated circuit comprising nonvolatile memory, the method comprising:

(a) forming, over a semiconductor region S1, a first layer, wherein the integrated circuit is to include a plurality of nonvolatile memory cells each of which has a floating gate comprising a portion of the first layer;

(b) forming trenches in the region S1 through openings in the first layer, and filling the trenches with insulation;

(c) forming a second layer over the region S1, wherein each of said cells is to have a conductive gate comprising a portion of the second layer, the conductive gate being insulated from the cell'"'"'s floating gate;

(d) patterning the second layer to form strips extending in a predetermined direction, each strip crossing over a plurality of trenches;

(e) removing that portion of the first layer over the region S1 which is not covered by the second layer, to form a plurality of first structures each of which comprises a strip made from the second layer and also comprises a portion of the first layer under the strip, each first structure having a first sidewall;

(f) forming a third layer over the first and second layers, and removing a portion of the third layer by a process comprising an anisotropic etch, to form a spacer over at least a portion of the first sidewall of each first structure, each spacer being insulated from materials of the first and second layers in the respective first structure;

(g) removing a portion of the third layer from over a portion of the region S1 so as not to completely remove said spacers, wherein each of said cells comprises a conductive gate comprising a portion of a spacer over a first sidewall of a first structure; and

(h) introducing dopant into at least a portion of the region S1;

wherein the operations (g) and (h) are performed using a single photolithographic masking operation performed before the operation (g).

2. The method of claim 1 wherein before the second layer is formed, the first layer forms strips extending at an angle to said predetermined direction, and the trenches extend through an array of nonvolatile memory cells in the same direction as the first layer strips.

3. The method of claim 2 wherein forming the first layer comprises photolithographic patterning of a mask over the first layer, the mask defining the strips of the first layer;

and

wherein the trenches are also defined by said mask.

4. The method of claim 1 wherein:

each first structure has a second sidewall; and

the photolithographic masking operation comprises depositing and photolithographically patterning a mask to overly at least portions of the spacers over the first sidewalls of the first structures and also overlying first semiconductor substrate regions between the first sidewalls of adjacent first structures; and

the operation (h) comprises introducing dopant into second semiconductor substrate regions between the second sidewalls of adjacent first structures.

5. The method of claim 4 wherein:

each second semiconductor substrate region extends between two adjacent first structures and provides source/drain regions for all of the memory cells that incorporate portions of the two adjacent first structures, which source/drain regions are to be electrically connected to each other.

6. The method of claim 4 further comprising completely or partially removing the insulation from the trenches at the location of the second semiconductor substrate regions by a masked etch using said mask.

7. The method of claim 6 further comprising, after the complete or partial removing of the insulation from the trenches, removing said mask and introducing dopant into the first and second semiconductor substrate regions.

8. The method of claim 1 wherein the first layer comprises a layer of polysilicon, and the second layer comprises a layer of polysilicon and a layer of conductive metal silicide.

9. The method of claim 1 wherein:

before the second layer is formed, the first layer has a plurality of rectangular openings but the first layer covers regions in which source lines are to be formed;

the trenches are formed by etching the semiconductor region S1 through the rectangular openings;

operation (e) comprises removing the first layer from over the source line regions.

10. A method for manufacturing an integrated circuit comprising a nonvolatile memory, the method comprising:

(a) forming insulation on a semiconductor region S1;

(b) forming, over the insulation, a plurality of conductive first strips of first material from which floating gates are to be formed, the first strips extending in a first direction;

(c) forming trenches in the semiconductor region S1, each trench extending between adjacent first strips of the first material, the trenches containing an insulator;

(d) forming insulation over the first strips;

(e) forming second material from which conductive memory gates are to be formed, wherein the second material is formed over the insulation formed over the first material;

(f) forming a mask over the second material, and patterning the second material using said mask, to form second strips of the second material, the second strips extending in a second direction at an angle to the first strips;

(g) removing that portion of the first material over the region S1 which is not covered by the second material, to form a plurality of first structures each of which comprises a second strip of the second material and also comprises floating gates formed from the first material under the second material, each first structure having a first sidewall;

(h) forming insulation over exposed sidewalls of the floating gates and of the second material in the first structures;

(i) forming a third material over the first and second materials, and removing a portion of the third material by a process comprising an anisotropic etch, to form spacers over at least portions of the first sidewalls of each first structure;

(j) forming a mask using photolithography, the mask covering the spacers over the first sidewalls of the first structures;

(j) removing the third layer by a process comprising an etch selective to said mask, so as not to remove the spacers which are to provide conductive gates for the nonvolatile memory; and

(k) introducing dopant into the region S1, wherein the dopant is blocked by said mask from portions of the region S1.

11. A method for manufacturing an integrated circuit comprising nonvolatile memory, the method comprising:

(a) forming over a semiconductor region S1, a first layer comprising a plurality of first strips extending in a first direction, wherein the memory is to include a plurality of nonvolatile memory cells each of which has a floating gate comprising a portion of the first layer;

(b) forming trenches in the semiconductor region S1, each trench extending in the first direction between adjacent first strips, the trenches containing an insulation;

(c) forming, over the first layer, a second layer, wherein each of said cells is to have a conductive gate comprising a portion of the second layer, the conductive gate being insulated from the cell'"'"'s floating gate, the second layer comprising a plurality of second strips extending at an angle to the first strips;

(d) removing that portion of the first layer over the region S1 which is not covered by the second layer, to form a plurality of first structures each of which comprises a second strip and also comprises a portion of the first layer under the second strip, each first structure having a first sidewall;

(f) forming a third layer over the first and second layers, and removing a portion of the third layer by a process comprising an anisotropic etch, to form spacers over at least portions of the first sidewalls of each first structure, each spacer being insulated from materials of the first and second layers in the respective first structure;

(g) removing the third layer so as not to remove the spacers, the spacers over the first sidewalls being to provide conductive gates for the nonvolatile memory cells;

(h) introducing dopant into a portion of the region S1, wherein a portion P1 of the insulation in the trenches is exposed to the dopant and impedes the dopant in reaching a trench surface;

(i) after the operation (h), removing from the trenches a part or all of said insulation portion P1; and

(j) after the operation (i), introducing dopant into at least a portion of the region S1 to dope at least portions of surfaces of the trenches.

12. The method of claim 11 wherein the semiconductor region S1 is a region of a first conductivity type which is electrically insulated from below by a region R1 of a second conductivity type;

and

wherein during the operation (h), the insulation in the trenches prevents the dopant introduced in the operation (h) from creating a short between a region doped during the operation (h) and the region R1.

14. The method of claim 13 wherein at least a portion of the first insulation is different in thickness from at least a portion of the second insulation.

15. The method of claim 13 wherein:

the integrated circuit comprises a third area in which a third MOS transistor is to be formed;

forming the first insulation comprises forming the first insulation in the third area;

before the layer L1 is formed, the first gate insulation is removed from the second and third areas and a third gate insulation is formed in the second and third areas;

when the layer L1 is removed from the second area, the layer L1 is also patterned in the first and third areas to provide conductive gates for the first and third MOS transistors.

16. The method of claim 15 wherein after the layer L2 has been formed, the first insulation thickness, the second insulation thickness, and the third gate insulation thickness are different from each other.

17. The method of claim 15 wherein the thickness of the first insulation in the first area increases when the third insulation is being formed.

18. The method of claim 13 wherein the integrated circuit comprises a nonvolatile memory cell which comprises (a) a conductive gate comprising a portion of the layer L1 and (b) a conductive gate comprising a portion of the layer L2.

19. The method of claim 18 further comprising:

before forming the first gate insulation, forming a gate insulation I1 on the semiconductor substrate for a nonvolatile memory cell to be formed in an area A1 of the integrated circuit;

before forming the first gate insulation, forming, over the insulation I1, a layer L3 to provide a floating gate for the memory cell;

before forming the first gate insulation, removing the layer L3 and the insulation I1 from the first and second areas.

20. The method of claim 19 further comprising forming an insulation over the layer L3 to insulate the layer L3 from the layer L1.

13. A method for manufacturing an integrated circuit, the method comprising:

forming a first gate insulation on a semiconductor substrate for a first MOS transistor which is to be formed in a first area of the integrated circuit;

forming, over the first insulation, a layer L1 to provide a conductive gate for the first MOS transistor;

removing the layer L1 and the first insulation from a second area of the integrated circuit;

forming a second gate insulation on the semiconductor substrate in the second area for a second MOS transistor;

forming, over the second insulation, a layer L2 to provide a conductive gate for the second MOS transistor.

21. A method for fabricating an integrated circuit comprising nonvolatile memory, the method comprising:

forming an insulation I1 to provide gate insulation for nonvolatile memory cells;

forming a first layer to provide floating gates for the memory cells;

removing the first layer and the insulation II from first, second and third areas of the integrated circuit, wherein at least one peripheral MOS transistor is to be formed in each of the first, second and third areas;

forming a first gate insulation in the first, second and third areas;

removing the first gate insulation from the second and third areas;

forming a second gate insulation in the second and third areas;

forming a second layer over the first layer, over the first gate insulation, and over the second gate insulation, wherein the memory cells and the MOS transistors in the first and third areas each have a conductive gate comprising a portion of the second layer;

removing the second layer from the second area;

forming a third gate insulation in the second area and in an area of the memory cells; and

forming a third layer, wherein the memory cells and the MOS transistor in the second area each comprises a conductive gate comprising a portion of the third layer,

wherein the first gate insulation in the first area is thicker than the second gate insulation and is thicker than the third gate insulation, and the third gate insulation is thicker than the second gate insulation.

22. An integrated circuit comprising:

at least one nonvolatile memory cell having a floating gate insulated from a semiconductor substrate, and having a control gate overlying the floating gate, and having another conductive gate;

a first peripheral transistor, a second peripheral transistor, and a third peripheral transistor;

wherein a gate insulation of the first peripheral transistor is thicker than a gate insulation of the second peripheral transistor which is thicker than a gate insulation of a third peripheral transistor.

25. The integrated circuit of claim 24 further comprising a second peripheral transistor having a gate formed from the layer L1.

30. The method of claim 29 wherein:

the operation (b) comprises depositing the second material, forming a mask over the second material, and etching the second material exposed by openings in the mask; and

the operation (c) comprises;

etching the semiconductor region S1 by a process selective to the mask and the first material as the mask remains in place, to form trenches in the regions bounded by the first and second strips; and

forming insulation in the trenches.

23. A method for manufacturing an integrated circuit comprising nonvolatile memory comprising a plurality of peripheral transistors, the method comprising:

forming a first layer over first, second and third areas of the integrated circuit, wherein the memory is to include at least one memory cell formed in the first area, at least one peripheral transistor in the second area, and at least one peripheral transistor in the third area, wherein the memory cell is to include a floating gate comprising a portion of the first layer;

removing the first layer from the second and third areas;

forming a second layer in the first, second and third areas, wherein the memory cell is to include a conductive gate comprising a portion of the second layer, and the peripheral transistor in the second area is to include a conductive gate comprising a portion of the second layer;

removing the second layer from the third area;

forming a third layer over the first and third areas, wherein the memory cell is to include a conductive gate comprising at least a portion of the third layer, and the peripheral transistor in the third area is to include a conductive gate comprising at least a portion of the third layer.

24. An integrated circuit comprising:

at least one nonvolatile memory cell having a floating gate insulated from a semiconductor substrate, and having a control gate overlying the floating gate, and having a conductive gate G1; and

a first peripheral transistor;

wherein the control gate is formed from a layer L1 and wherein the gate G1 and a gate of the first peripheral transistor are formed from a different layer L2.

26. A method for manufacturing an integrated circuit comprising a nonvolatile memory array and a peripheral transistor used to operate the memory array, the method comprising:

forming, over a semiconductor substrate, a first layer to provide floating gates for the memory array;

forming, over the semiconductor substrate, a second layer overlying the first layer but insulated from the first layer, to provide conductive memory gates for the memory array;

so that the first and second layers are present over a region S1 of the semiconductor substrate, the region S1 being where the memory array is to be formed, but the first and second layers are not present over a region S2 of the semiconductor substrate, the region S2 being where a peripheral transistor for a peripheral circuitry is to be formed;

after forming the first and second layers, forming a third layer over the semiconductor substrate to provide conductive gates for the memory array, wherein each nonvolatile memory cell of the memory array has a conductive gate formed from the second layer and has a conductive gate formed from the third layer;

wherein a portion of the third layer is present over the region S2 to provide at least a portion of a conductive gate of the peripheral transistor.

27. A method for manufacturing an integrated circuit comprising nonvolatile memory, the method comprising:

forming, over a semiconductor substrate, a first layer to provide floating gates for the memory array;

forming, over the semiconductor substrate, a second layer overlying the first layer but insulated from the first layer, wherein the memory is to have a plurality of conductive gates each of which comprises a portion of the second layer;

patterning the second layer to provide at least one structure comprising a strip of the second layer and also comprising floating gates under the strip of the second layer, the floating gates being formed from the first layer, wherein the memory is to have a plurality of cells each of which comprises a conductive gate comprising a portion of the strip of the second layer, wherein the structure has a sidewall;

depositing a third layer over said structure, wherein each of said cells is to have a conductive gate comprising a portion of the third layer and formed over the sidewall of said structure;

forming a mask over the third layer, and etching the third layer anisotropically to provide a spacer line over the sidewall of said structure in a region not covered by the mask, wherein each of said cells is to have a conductive gate comprising a portion of said spacer line, wherein a third layer portion covered by the mask comprises extensions to the spacer line;

forming an insulator over the first, second and third layers, and forming a conductive layer contacting the extension through openings in the insulator.

28. An integrated circuit comprising nonvolatile memory comprising:

a structure comprising a conductive line L1 providing first conductive gates for a plurality of memory cells, the structure also comprising a plurality of floating gates formed under the conductive line L1 and insulated from the conductive line L1;

a conductive line L2 formed as a spacer on a sidewall of said structure and providing second conductive gates for said memory cells, each of said memory cells comprising one of said first conductive gates and one of said second conductive gates;

wherein said structure, said floating gates, and said conductive lines L1 and L2 are formed over a semiconductor substrate;

wherein the substrate comprises;

a plurality of trenches formed therein and extending at an angle to said structure; and

a conductive area extending along said structure traversing a plurality of said trenches, the conductive area providing source/drain regions for said memory cells.

29. A method for manufacturing an integrated circuit comprising nonvolatile memory, the method comprising:

(a) forming over a semiconductor region S1, a plurality of first strips of a first material from which floating gates are to be formed, the first strips extending in a first direction;

(b) forming over the semiconductor region S1, a plurality of second strips of a second material, the second strips extending in a second direction at an angle to the first direction, thereby creating regions bounded by the first and second strips;

(c) forming trenches in the region S1 in the areas bounded by the first and second strips, and filling the trenches with insulation;

(d) forming a material L1 from which conductive memory gates are to be formed, wherein the material L1 is formed over the first material, and is insulated from the first material;

(e) forming a mask over the material L1, and patterning the material L1 using said mask, so that the material L1 is removed from over at least a portion of each of the first strips;

(f) removing the first material not covered by the material L1 over the region S1, to form a plurality of first structures each of which includes the first material and the material L1 overlying the first material;

(g) insulating at least one sidewall of each first structure;

(h) forming a third material over the first material and the material L1;

(i) etching the third material by a process comprising an anisotropic etch, to form a spacer on at least one sidewall of each of the first structures; and

(j) doping at least portions of those areas of the region S1 over which the first material has been removed and of those areas of the region S1 over which the second strips were formed;

wherein the nonvolatile memory comprises floating gate regions formed from the first material, conductive gate regions formed from the material L1, and conductive gate regions formed from the third material.

31. A method for manufacturing an integrated circuit comprising nonvolatile memory, the method comprising:

(a) forming, over a semiconductor region S1, a first layer, wherein the integrated circuit is to include a plurality of nonvolatile memory cells each of which has a floating gate comprising a portion of the first layer;

(b) forming trenches in the region S1 through openings in the first layer, and filling the trenches with insulation;

(c) forming a second layer over the region S1, wherein each of said cells is to have a conductive gate comprising a portion of the second layer, the conductive gate being insulated from the cell'"'"'s floating gate;

(d) patterning the second layer to form strips extending in a predetermined direction, each strip crossing over a plurality of trenches;

(e) removing that portion of the first layer over the region S1 which is not covered by the second layer, to form a plurality of first structures each of which comprises a strip made from the second layer and also comprises a portion of the first layer under the strip, each first structure having a first sidewall;

(f) forming a third layer over the first and second layers, and removing a portion of the third layer by a process comprising an anisotropic etch, to form a spacer over at least a portion of the first sidewall of each first structure, each spacer being insulated from materials of the first and second layers in the respective first structure;

(g) removing a portion of the third layer from over a portion of the region S1 so as not to completely remove said spacers, wherein each of said cells comprises a conductive gate comprising a portion of a spacer over a first sidewall of a first structure; and

(h) introducing dopant into at least a portion of the region S1.

32. A method for erasing memory cells of a flash memory array formed in and over a semiconductor region, the memory array comprising a plurality of sections each of which can be erased individually, each section having a plurality of memory cells, the method comprising:

receiving by the memory a command indicating whether the entire memory array is to be erased or less than the entire memory array is to be erased;

if the entire memory array is to be erased, then erasing the entire memory array;

if less than the entire memory array is to be erased, then erasing a portion of the memory array without erasing the entire memory array.

33. The method of claim 32 wherein erasing the entire memory array comprises providing a first voltage to the semiconductor region and a second voltage to all of control gates of the memory array.

34. The method of claim 32 wherein erasing a portion of the memory array comprises:

providing a first voltage to control gates of memory cells in said portion;

providing a second voltage to control gates of memory cells in the array outside of said portion.

35. The method of claim 32 wherein erasing the entire memory array comprises erasing a memory cell by Fowler-Nordheim tunneling from the cell'"'"'s floating gate to the cell'"'"'s channel region located in the semiconductor region.

36. The method of claim 32 wherein erasing the portion of the memory array comprises erasing a memory cell by Fowler-Nordheim tunneling from the cell'"'"'s floating gate to the cell'"'"'s channel region located in the semiconductor region.

37. The method of claim 32 wherein erasing the portion of the memory array comprises erasing a memory cell by Fowler-Nordheim tunneling from the cell'"'"'s floating gate to the cell'"'"'s source/drain region located in the semiconductor region.

38. A method for forming an integrated circuit comprising nonvolatile memory, the method comprising:

forming a first layer over a semiconductor region S1 of a semiconductor substrate, wherein the integrated circuit comprises a plurality of memory cells each of which comprises a floating gate comprising a portion of the first layer;

forming a second layer over the first layer and over the semiconductor region S1, and forming a layer C1 over the second layer, wherein each memory cell comprises a conductive gate comprising a portion of the second layer and insulated from the cell'"'"'s floating gate;

forming a third layer, wherein each memory cell comprises a conductive gate comprising a portion of the third layer, and wherein a peripheral transistor comprises a conductive gate formed from a portion of the third layer;

wherein the second layer comprises a dummy portion adjacent the conductive gate of the peripheral transistor, and the layer C1 comprises a portion on top of the dummy portion of the second layer;

the method further comprising forming insulation over the layer C1 and the first and second layers and polishing said insulation by a process that stops at the layer C1, the portion of the layer C1 over the dummy portion of the second layer protecting, during the polishing process, the third layer portion present in the conductive gate of the peripheral transistor.