Method and circuit for deriving a second clock signal from a first clock signal

• US 20020039396A1
• Filed: 10/02/2001
• Published: 04/04/2002
• Est. Priority Date: 10/02/2000
• Status: Active Grant

• Current Assignee: Lenovo Innovations Ltd Hong Kong (Lenovo Group Ltd.)
• Original Assignee: NEC Corporation
• Inventors: Zalio, Filip
• Granted Patent: US 7,248,658 B2
• Time in Patent Office: Days
• US Class Current: 375/355
• CPC Class Codes: G06F 1/0328 in which the phase increment is adjustable, e.g. by using an adder-accumulator

Abstract

A clock generation circuit (21) for a dual system radio frequency (RF) station, including:

a digital synthesis circuit (20) clocked by a first clock signal for one RF system and adapted to generate an output having a base signal of a predetermined frequency; and

filter means (31) for deriving a second clock signal for another RF system from a signal of said output, said signal having a frequency corresponding to the frequency of said second clock signal.

Claims

1. A clock generation circuit for a dual system radio frequency (RF) station, including:

a digital synthesis circuit clocked by a first clock signal for one RF system and adapted to generate an output having a base signal of a predetermined frequency; and

filter means for deriving a second clock signal for another RF system from a signal of said output, said signal having a frequency corresponding to the frequency of said second clock signal.

2. A clock generation circuit according to claim 1, wherein said signal is an artefact of said output.

3. A clock generation circuit according to either one of claims 1 or 2, wherein said signal is a Nyquist image of said output.

4. A clock generation circuit for a dual system radio frequency (RF) station, including:

a digital synthesis circuit clocked by a first clock signal for one RF system and adapted to generate an output having a base signal of a predetermined frequency; and

a filter for filtering a Nyquist image of said output, said Nyquist image having a frequency being the sum of the frequency of the first clock signal and the predetermined frequency, and being the frequency of a second clock signal for another RF system.

5. A method for deriving a second clock signal from a first clock signal, where the frequency of said second clock signal is greater than half the frequency of said first clock signal, including the steps of:

clocking a direct digital synthesis circuit with said first clock signal;

applying a phase step in said synthesis circuit such that a signal generated by said circuit has the frequency of said second clock signal; and

filtering the output of said synthesis circuit to select said signal.

6. A method for deriving a second clock signal from a first clock signal according to claim 5, wherein the frequency of said second clock signal is greater than the frequency of said first clock signal.

7. A method for deriving a second clock signal from a first clock signal according to either one of claims 5 or 6, wherein the frequencies of said clock signals are those used by different radio frequency communications systems.

8. A method for deriving a second clock signal from a first clock signal according to any one of claims 5 to 7, wherein said phase step is such that a base signal frequency generated by said circuit represents the difference in frequency between said first clock signal and said second clock signal.