Image processor

• US 20020039453A1
• Filed: 08/29/2001
• Published: 04/04/2002
• Est. Priority Date: 09/01/2000
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Miyamura, Makoto, Nishide, Hiroshi, Naiki, Takashi
• Granted Patent: US 6,898,330 B2
• Time in Patent Office: Days
• US Class Current: 382/274
• CPC Class Codes: G06T 5/50 using two or more images, e.g. averaging or subtraction
• CPC Class Codes: G06T 5/92 based on global image properties
• CPC Class Codes: H04N 1/4072 dependent on the contents of the original
• CPC Class Codes: H04N 23/76 by influencing the image signals
• CPC Class Codes: H04N 23/88 for colour balance, e.g. white-balance circuits or colour temperature control
• CPC Class Codes: H04N 5/20 Circuitry for controlling amplitude response

Abstract

An image processor for forming an easy-to-see image by broadening the significant band of image data received from a logarithmic (LOG) image sensor to enhance the contrast of the image. The LOG image sensor generates an output in response to the light, with the output voltage being a logarithm of the intensity of the light received. The image processor extracts only those pixel data in the significant band out the image data received from the LOG image sensor in accordance with the distribution of the voltage of the signals. In order to form an easy-to-see image, the processor expands the voltage band, assuming that the output voltage has a linear dependence on the intensity of light received by the LOG image sensor. The resultant image has an wider band in voltage, which enhances the contrast, and hence the visibility, of the image.

Claims

1. An image processor comprising:

voltage band determination means for determining a voltage band for an image to be displayed which are generated by an image sensor outputting a compressed image (compressive image sensor) in response to the light received by said compressive image sensor; and

image conversion means for converting said voltage band by expanding said band, assuming the voltage to depend linearly on the intensity of light over said voltage band.

2. The image processor according to claim 1, wherein said compressive image sensor is a logarithmic conversion image sensor.

3. The image processor according to claim 1, wherein said image conversion means further comprises:

subtraction means for subtracting the lower limit of said voltage band from said voltage band so as to match the lower limit of said subtracted band with a prescribed post-conversion minimum Lmin; and

multiplication means for converting said subtracted band so as to match the upper limit of the converted band with a prescribed post-conversion maximum Lmax.

4. The image processor according to claim 1, wherein said image conversion means further comprises:

multiplication means for matching the upper limit of said voltage width with a given post-conversion maximum Lmax; and

operational means for matching the lower limit of the multiplied voltage width with a given post-conversion minimum Lmin.

5. An image processor comprising:

first conversion means for obtaining first conversion data D′

for the entire pixel data D lying within a significant voltage band Dmin-Dmax by

(i) constructing a ratio R of the sum of the assessment pixel data belonging to an assessment area that precedes currently processing pixel data D to the sum of said assessment pixel data summed on the assumption that all of said assessment pixel data have maximum possible values,

(ii) multiplying each of the pixel data D by said ratio R and a first predetermined coefficient A, and

(iii) replacing by a prescribed post-conversion maximum Lmax those pixel data that exceed said maximum Lmax upon multiplication of said ratio R and said coefficient A; and

second conversion means for obtaining second conversion data D″

by

(iv) subtracting each of said pixel data D′

from post-conversion maximum Lmax,

(v) multiplying each of the subtracted data of (i) by a second predetermined coefficient B,

(vi) replacing by said post-conversion maximum Lmax those pixel data that exceed said post-conversion maximum Lmax upon multiplication of said coefficient B, and

(vii) subtracting again from said post-conversion maximum Lmax each of the data that result from the foregoing steps (iv)-(vi).

6. The image processor according to claim 5, wherein said first conversion means has a feedback loop to decrease said first coefficient A by a predetermined magnitude when the number of the pixel data replaced by said post-conversion maximum Lmax is greater than a predetermined number N1, but increment said coefficient A by a predetermined magnitude when said replaced number of pixel data is less than a predetermined number N2.

7. The image processor according to claim 5, wherein said second conversion means has a feedback loop to decrease said second coefficient B by a predetermined magnitude when the number of pixel data replaced by said post-conversion maximum Lmax is greater than a predetermined number N3, but increment said coefficient B by a predetermined magnitude when said replaced number of pixel data is less than a predetermined number N4.

8. The image processor according to claim 5, wherein

said second Lmax is replaced by Lmax′

=Lmax−

Lmin in said first and said second conversion means when said minimum Lmin is a positive/negative number (other than zero); and

said second conversion means is adapted to output the sum of said second converted pixel data D″ and

Lmin.

9. The image processor according to claim 8, adapted to subtract said post-conversion minimum Lmin from all of the pixel data D prior to said first conversion.

10. An image processor, comprising:

first conversion means for converting all the pixel data D lying in a voltage band in a range Dmin-Dmax to obtain first converted pixel data D′

by

(i) multiplying said pixel data D by a third coefficient C1 having a predetermined initial value,

(ii) replacing those converted pixel data that exceed a prescribed post-conversion maximum Lmax by Lmax; and

second conversion means for obtaining second conversion data D″

by

(iii) subtracting each of said first converted pixel data D′

from said post-conversion maximum Lmax,

(iv) multiplying the result of said subtraction in (iii) by a fourth multiplication coefficient C2,

(v) replacing by said post-conversion maximum Lmax those pixel data that exceed Lmax upon multiplication of C2 in (iv), and

(vi) again subtracting from Lmax each of the resultant pixel data obtained in steps (iii)-(v).

11. The image processor according to claim 10, wherein said first conversion means has a feedback loop to decrease said third coefficient C1 by a predetermined magnitude when the number of pixel data replaced by said post-conversion maximum Lmax is greater than a predetermined number N1, but increment said coefficient C1 by a predetermined magnitude when said replaced number of pixel data is less than a predetermined number N2.

12. The image processor according to claim 10, wherein said second conversion means has a feedback loop to decrease said fourth coefficient C2 by a predetermined magnitude when the number of pixel data replaced by said post-conversion maximum Lmax is greater than a predetermined number N3, but increment said coefficient C2 by a predetermined magnitude when said replaced number of pixel data is less than a predetermined number N4.

13. The image processor according to claim 10, wherein

said first and said second conversion means are adapted to replace said post-conversion maximum Lmax by a modified post-conversion maximum defined by Lmax′

=Lmax−

Lmin when said post-conversion minimum Lmin is not zero, and wherein

said second conversion means is further adapted to add said post-conversion minimum Lmin to said second converted pixel data D″

.

14. The image processor according to claim 13, adapted to subtract said post-conversion minimum Lmin from all of the pixel data D prior to said first conversion.