Multiprocessor system and transaction control method for the same
First Claim
1. A processor system, comprising:
- at least one processor;
a node controller unit connected to said at least one processor via a processor bus;
at least one I/O unit having an I/O bus;
at least one memory, and a network connecting each of said memories, said node controller unit, and each of said I/O units;
wherein each of said I/O units is adapted to consecutively issue a successive transaction to any of said memories or any of said processors before a preceding transaction has been processed;
further wherein said node controller unit, when said memory or said processor retries and suspends the reply to said preceding transaction issued from said I/O bus, causes said I/O unit to suspend the reply to said successive transaction or request the retry of and reissue said successive transaction.
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Accused Products
Abstract
A processor system and method whereby a successive transaction which depends upon a preceding transaction is sent without waiting for the completion of the preceding transaction issued from an I/O bus to a memory. A source side I/O unit consecutively issues transactions from an I/O bus. A reply side node controller unit or transfer unit has an I/O flag register for recording a reply-requested or reply-pending preceding transaction to assure transactions from the same I/O bus are sequentially completed according to certain bus protocols. Consequently, the reply side node controller unit or transfer unit retries or suspends the reply to the successive transaction, when retry of a preceding transaction is requested or its reply is suspended. Various internal registers and counters may be used.
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Citations
27 Claims
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1. A processor system, comprising:
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at least one processor;
a node controller unit connected to said at least one processor via a processor bus;
at least one I/O unit having an I/O bus;
at least one memory, and a network connecting each of said memories, said node controller unit, and each of said I/O units;
wherein each of said I/O units is adapted to consecutively issue a successive transaction to any of said memories or any of said processors before a preceding transaction has been processed;
further wherein said node controller unit, when said memory or said processor retries and suspends the reply to said preceding transaction issued from said I/O bus, causes said I/O unit to suspend the reply to said successive transaction or request the retry of and reissue said successive transaction. - View Dependent Claims (2, 6, 8, 10, 12, 14, 22)
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3. A processor system, comprising:
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at least one processor;
a node controller unit connected to said at least one processor via a processor bus;
at least one I/O unit having an I/O bus;
at least one memory, and a network connecting each of said memories, said node controller unit, and each of said I/O units;
wherein each of said I/O units is adapted to consecutively issue a successive transaction to any of said memories or any of said processors before a preceding transaction has been processed;
further wherein a transfer unit in said network, when said memory or said processor retries said preceding transaction issued from said I/O bus, causes said I/O unit to request the retry of and reissue said successive transaction, said transfer unit not being located in said node controller unit. - View Dependent Claims (4, 5, 7, 9, 11, 13, 15, 16, 17, 18, 19, 20, 21, 23, 24, 25, 26, 27)
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Specification