Multiple trap avoidance mechanism

• US 20020040450A1
• Filed: 02/13/2001
• Published: 04/04/2002
• Est. Priority Date: 10/03/2000
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Durrant, Paul, Harris, Jeremy Graham
• Granted Patent: US 6,795,937 B2
• Time in Patent Office: Days
• US Class Current: 714/8
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

To provide efficient resource access control in a computer system, a trap handler for handling a trap in the event of a faulty resource access being detected is arranged to define a diversion for subsequent access attempts to the same resource. An address translation mechanism is responsive to indication of a diversion for a resource access to modify an address mapping, whereby subsequent attempts to access the resource are diverted in accordance with the diversion. The trap handler can be arranged in a conventional manner to process an exception of the first faulty access to the resource. However, by defining the diversion, which can be used to map further attempts to access the same resource, unnecessary exception processing can be avoided.

Claims

1. A resource access control mechanism for a computer system including at least one central processing unit, the resource access control mechanism comprising an address translation mechanism operable to map a received address to a resource and a trap handler for handling a trap in the event of a faulty resource access being detected, the trap handler being operable to instigate a diversion for subsequent access attempts to the resource and the address translation mechanism being responsive to instigation of a diversion by the trap handler to effect the diversion for subsequent attempts to access the resource.

2. The resource access control mechanism of claim 1, wherein the trap handler is further operable to process an exception.

3. The resource access control mechanism of claim 1 or claim 2, wherein the address translation mechanism includes a translation look-aside buffer.

4. The resource access control mechanism of any preceding claim, wherein the address translation mechanism forms part of a memory management unit.

5. The resource access control mechanism of any preceding claim, wherein the trap handler is operable to identify an alternative resource address to the address translation mechanism for replacing a resource address held in an address translation entry for the resource.

6. The resource access control mechanism of any of claims 1 to 4, wherein the trap handler is operable to instigate the diversion by signaling the address translation mechanism.

7. The resource access control mechanism of claim 6, wherein the address translation mechanism is responsive to instigation of a diversion by the trap handler to replace a resource address held in an address translation entry for the resource with an alternative resource address.

8. The resource access control mechanism of claim 6, wherein the address translation mechanism is responsive to instigation of a diversion by the trap handler to set a divert flag in a translation entry of the address translation and is further operable to respond to a received address relating to an address translation entry having a divert flag set to use an alternative address to that held in the address translation entry.

9. The resource access control mechanism of claim 6, wherein the address translation mechanism is responsive to instigation of a diversion by the trap handler to set a divert flag in a translation entry of the address translation and is further operable to respond to a received address relating to an address translation entry having a divert flag set to modify an address held in the address translation entry.

10. The resource access control mechanism of any preceding claim, wherein the resource is at least one memory location.

11. The resource access control mechanism of any of claims 1 to 9, wherein the resource is a peripheral device.

12. The resource access control mechanism of any of claims 1 to 9, wherein the resource is a subsystem.

13. The resource access control mechanism of any preceding claim, wherein the alternative resource is a faked response generator.

14. The resource access control mechanism of any of claims 1 to 12, wherein the alternative resource is a predefined memory portion.

15. A computer system comprising at least one processor that includes at least one central processing unit, memory, at least one peripheral device and the resource access control mechanism of any preceding claim.

16. The computer system of claim 15, operable to identify an initial faulty access to a resource.

18. The method of claim 17, further comprising processing an exception.

19. The method of claim 17 or claim 18, wherein the defining of a diversion includes replacing a resource address held in an address translation entry for the resource with an alternative resource address.

20. The method of claim 17 or claim 18, wherein the defining of a diversion includes setting a divert flag in an address translation entry for the resource and the diverting of a subsequent attempt to access the resource includes using an different address to that held in the address translation entry when the divert flag is set.

21. The method of claim 17 or claim 18, wherein the defining of a diversion includes setting a divert flag in an address translation entry for the resource and the diverting of a subsequent attempt to access the resource includes modifying an address held in the address translation entry.

27. A computer program forming a trap handler for a computer system according to claim 15, the computer program comprising computer code operable:

to respond to a faulty resource access by processing an exception; and

to instigate a diversion in an address translation mechanism for subsequent access attempts to the resource.

17. A method of managing processor access to resources in a computer system, the method comprising:

handling a trap in the event of an initial faulty access attempt to a resource being detected;

defining a diversion for subsequent access attempts to the same resource;

diverting a subsequent attempt to access the resource.

22. The method of any of claims 17 to 21, wherein the diversion is to a predefined memory portion.

23. The method of any of claims 17 to 21, wherein the diversion results in the generation of a faked response to the resource access.

24. The method of any of claims 17 to 23, wherein the resource is at least one memory location.

25. The method of any of claims 17 to 23, wherein the resource is a peripheral device.

26. The method of any of claims 17 to 23, wherein the resource is a subsystem.

28. A computer program product comprising the computer program of claim 23, wherein said program code is carried by a carrier medium.