Phase-locked loop

• US 20020041215A1
• Filed: 02/14/2001
• Published: 04/11/2002
• Est. Priority Date: 12/22/1998
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Kiyose, Masashi
• Granted Patent: US 6,515,520 B2
• Time in Patent Office: Days
• US Class Current: 331/57
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO) and a pair of charge pump circuits (CP) and provides a stable oscillation clock signal. A phase comparator compares a reference clock signal with an oscillation clock signal generated by the VCO and generates two comparison signals. The comparison signals are input to the first CP, which generates a first CP output signal. The first CP output signal is filtered with a first low pass filter (LPF) and the filtered signal (control voltage) is provided to the VCO, which produces the oscillation clock. The second CP receives two clock signals and generates a second CP output signal. The second CP output signal is filtered with a second LPF and the filtered signal is converted to a digital signal with an A/D converter. The digital signal is applied to a bias circuit, which then produces first and second control voltages. These control voltages are then applied to the first and second CPs to control the charging and discharging currents of the CPs.

Claims

1. A phase-locked loop comprising:

a voltage-controlled oscillator for generating an oscillation output signal having a frequency corresponding to a control voltage;

a phase comparator connected to the voltage-controlled oscillator for comparing a phase of the oscillation output signal and a phase of a reference clock signal to generate a comparison output signal;

a first charge pump circuit connected to the phase comparator for generating a first charge pump output signal in accordance with the comparison output signal;

a first low-pass filter connected to the first charge pump circuit for smoothing the first charge pump output signal and generating the control voltage;

a second charge pump circuit for generating a second charge pump output signal;

a second low-pass filter connected to the second charge pump circuit for smoothing the second charge pump output signal and generating a compensation voltage; and

a control circuit connected to the second low-pass filter for controlling the first and second charge pump circuits to adjust the first and second charge pump output signals in accordance with the compensation voltage.

2. The phase-locked loop according to claim 1, wherein the control circuit includes a compensation information generating circuit for generating compensation information in accordance with the compensation voltage, generating a bias control voltage in accordance with the compensation information, and providing the bias control voltage to the first and second charge pump circuits, and wherein the first and second charge pump circuits generate the first and second charge pump output signals in accordance with the bias control voltage.

3. The phase-locked loop according to claim 2, wherein the compensation information generating circuit includes an A/D converter for converting the compensation voltage to a digital value in order to generate the compensation information.

4. The phase-locked loop according to claim 2, wherein the compensation information generating circuit includes:

a voltage comparator for comparing the compensation voltage and a reference voltage and generating a comparison signal; and

an up and down counter connected to the voltage comparator for performing up count or down count in accordance with the comparison signal in order to generate the compensation information.

5. The phase-locked loop according to claim 1, wherein the control circuit includes:

a compensation information generating circuit for generating compensation information according to the compensation voltage; and

a bias control circuit connected to the compensation information generating circuit for generating a bias control voltage in accordance with the compensation information and providing the bias control voltage to the first and second charge pump circuits, the first and second charge pump circuits generating the respective first and second charge pump output signals in accordance with the bias control voltage.

6. The phase-locked loop according to claim 5, wherein the compensation information generating circuit includes an A/D converter for converting the compensation voltage to a digital value in order to generate the compensation information.

7. The phase-locked loop according to claim 5, wherein the compensation information generating circuit includes:

a voltage comparator for comparing the compensation voltage and a reference voltage and generating a comparison signal; and

an up and down counter connected to the voltage comparator for performing up count or down count in accordance with the comparison signal in order to generate the compensation information.

8. A charge pump circuit comprising:

a p-channel drive transistor and an n-channel drive transistor connected in series between a high potential power supply and a low potential power supply, wherein input signals are respectively applied to a gate of the p-channel drive transistor and a gate of the n-channel drive transistor in order to generate a charge pump output signal at a node between the p-channel and n-channel drive transistors;

a p-channel current control transistor connected between the p-channel drive transistor and the node; and

an n-channel current control transistor connected between the n-channel drive transistor and the node, wherein compensation voltages are respectively applied to a gate of the p-channel current control transistor and a gate of the n-channel current control transistor.

9. The charge pump circuit according to claim 8, wherein the compensation voltages are set in accordance with changes in characteristics of each of the transistors.

10. The charge pump circuit according to claim 8, wherein the compensation voltages are set in accordance with fluctuations in the voltage of the high potential power supply.

11. The charge pump circuit according to claim 8, further comprising:

a first transistor and a resistor connected in series between the high potential power supply and the low potential power supply; and

a second transistor and a third transistor connected in series between the high potential power supply and the low potential power supply, wherein a gate of the first transistor and a gate of the second transistor are connected to a first node between the first transistor and the resistor, and a gate of the third transistor is connected to a second node between the second and third transistors, wherein the first compensation voltage is applied to one of the gates of the p-channel and n-channel current control transistors, and a second compensation voltage is applied to the other one of the gates of the p-channel and n-channel current control transistors.

12. The charge pump circuit according to claim 11, further comprising a fourth transistor connected in parallel to the third transistor, wherein a control voltage is applied to a gate of the fourth transistor in order to adjust the second compensation voltage.

15. The voltage-controlled oscillator according to claim 14, wherein the oscillation circuit includes:

an odd number of CMOS inverters connected in series, the output of the final inverter being fed back to the input of the first inverter;

a plurality of first current control transistor respectively connected between the CMOS inverters and a high potential power supply, the first control voltage being applied to a gate of each of the first current control transistors; and

a plurality of second current control transistors respectively connected between each of the CMOS inverters and a low potential power supply, the second control voltage being applied to a gate of each of the second current control transistors.

16. The voltage-controlled oscillator according to claim 15, wherein the level shift circuit includes:

a depletion transistor connected to one of the high potential and low potential power supplies, wherein the initial control voltage is applied to a gate of the depletion transistor;

a resistor string connected in series between the depletion transistor and the other one of the high and low potential power supplies to generate a plurality of divisional voltages by dividing the voltage between the high potential and low potential power supplies; and

a decoder for selecting one of the plurality of divisional voltages in accordance with the adjustment information, the selected divisional voltage being provided to the oscillation circuit as the first control voltage; and

wherein the compensation circuit includes,

a resistor and a first transistor connected in series between the high potential power supply and the low potential power supply;

a second transistor and a third transistor connected in series between the high potential power supply and the low potential power supply; and

a fourth transistor connected in parallel to the second transistor, wherein a gate of the first transistor, a gate of the second transistor, and a gate of third transistor are connected to a first node between the resistor and the first transistor, and a gate of the fourth transistor is connected to a second node between the second and third transistors, the second control voltage being provided to the oscillation circuit from the second node.

13. A charge pump circuit comprising:

a p-channel drive transistor and an n-channel drive transistor connected in series between a high potential power supply and a low potential power supply, wherein input signals are respectively applied to a gate of the p-channel drive transistor and a gate of the n-channel drive transistor in order to generate a charge pump output signal at a node between the p-channel and n-channel drive transistors;

a p-channel current control transistor connected between the p-channel drive transistor and the node;

an n-channel current control transistor connected between the n-channel drive transistor and the node;

a first transistor and a resistor connected in series between the high potential power supply and the low potential power supply;

a second transistor and a third transistor connected in series between the high potential power supply and the low potential power supply; and

a fourth transistor connected in parallel to the third transistor, wherein a gate of the first transistor, a gate of the second transistor, and one of a gate of the p-channel current control transistor and a gate of the n-channel current control transistor are connected to a first node between the first transistor and the resistor, and a gate of the third transistor and the gate of the other one of the p-channel and n-channel current control transistors are connected to a second node between the second and third transistors, and wherein a control voltage is applied to a gate of the fourth transistor.

14. A voltage-controlled oscillator comprising:

an oscillation circuit for generating an oscillation output signal, having a predetermined frequency, in accordance with first and second control voltages;

a level shift circuit connected to the oscillation circuit for generating the first control voltage by shifting an initial control voltage in accordance with adjustment information and providing the first control voltage to the oscillation circuit; and

a compensation circuit connected to the oscillation circuit for providing the second control voltage to the oscillation circuit in accordance with changes in the operational environment, wherein the oscillation circuit sets an oscillation frequency band of the oscillation output signal in accordance with the first control voltage.

17. A phase-locked loop comprising:

a voltage-controlled oscillator for generating an oscillation output signal having a frequency corresponding to a control voltage;

a phase comparator connected to the voltage-controlled oscillator for comparing a phase of the oscillation output signal and a phase of a reference clock signal to generate a comparison output signal;

a first charge pump circuit connected to the phase comparator for generating a first charge pump output signal in accordance with the comparison output signal;

a first low-pass filter connected to the first charge pump circuit for smoothing the first charge pump output signal and generating the control voltage;

a second charge pump circuit for generating a second charge pump output signal;

a second low-pass filter connected to the second charge pump circuit for smoothing the second charge pump output signal and generating a compensation voltage; and

a control circuit connected to the second low-pass filter for controlling the first and second charge pump circuits to adjust the first and second charge pump output signals in accordance with the compensation voltage;

wherein at least one of the first and second charge pump circuits includes,

a p-channel drive transistor and an n-channel drive transistor connected in series between a high potential power supply and a low potential power supply, wherein the comparison output signal is applied to a gate of the p-channel drive transistor and a gate of the n-channel drive transistor in order to output a relative charge pump output signal from a node between the p-channel and n-channel drive transistors;

a p-channel current control transistor connected between the p-channel drive transistor and the node; and

an n-channel current control transistor connected between the n-channel drive transistor and the node, wherein an adjustment voltage is applied to a gate of the p-channel current control transistor and a gate of the n-channel current control transistor; and

wherein the voltage-controlled oscillator includes,

an oscillation circuit for generating the oscillation output signal in accordance with the control voltage, wherein the control voltage includes a first control voltage and a second control voltage, wherein the oscillation circuit sets an oscillation frequency band of the oscillation output signal in accordance with the first control voltage;

a level shift circuit connected to the oscillation circuit for generating the first control voltage by shifting an initial control voltage in accordance with adjustment information and providing the first control voltage to the oscillation circuit; and

a compensation circuit connected to the oscillation circuit for adjusting the second control voltage in accordance with changes in the operational environment, wherein the oscillation circuit sets an oscillation frequency band of the oscillation output signal in accordance with the first control voltage.