Method and apparatus for vertically locking input and output signals
First Claim
1. A method for vertically locking signals comprising:
- obtaining input signal having input vertical sync pulse;
generating a pixel clock frequency from a reference frequency;
determining output vertical sync pulse from said pixel clock frequency;
generating said reference frequency to obtain a lock between said input vertical sync pulse and said output vertical sync pulse.
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Abstract
This invention describes a method and apparatus for vertically locking input and output video frame rates. The output vertical sync pulse is locked in phase with the input vertical sync pulse, regardless of the input format and frequency. The output resolution, horizontal refresh rate, and delay are all user selectable. Two Phase Locked Loops are connected in series to achieve vertical lock between the input and output frames. Locking the vertical sync pulses between the input and output frames will eliminate mixing of pixels from different input frames in one output frame. The first Phase Locked Loop generates the output pixel clock required to satisfy the user'"'"'s display preferences but may not precisely represent the desired output pixel clock required for frame locking because current Phase Locked Loops use integer dividers. A second Phase Locked Loop adjusts its output, which is the reference frequency to the first Phase Locked Loop, until a lock is achieved. A free running oscillator measures the frequency of the incoming video and sends its output to a micro-controller that computes the divider required in the first Phase Locked Loop based on user selected output resolution. The user may also adjust the delay between the vertical input and output video frames.
44 Citations
25 Claims
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1. A method for vertically locking signals comprising:
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obtaining input signal having input vertical sync pulse;
generating a pixel clock frequency from a reference frequency;
determining output vertical sync pulse from said pixel clock frequency;
generating said reference frequency to obtain a lock between said input vertical sync pulse and said output vertical sync pulse. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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13. A system for vertically locking signals comprising:
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an input signal comprising input vertical sync pulses;
a clock generator for generating clock pulses from a reference frequency;
an output timing generator for generating output vertical sync pulses from said clock pulses;
a detector coupled to said output timing generator and said input signal for comparing said output vertical sync pulses and said input vertical sync pulses; and
an adjuster coupled to said detector, said adjuster configured to adjust said clock pulses by adjusting said reference frequency so that said input vertical sync pulses and said output vertical sync pulses are synchronized.
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Specification