Method and apparatus for vertically locking input and output signals

• US 20020041335A1
• Filed: 08/14/2001
• Published: 04/11/2002
• Est. Priority Date: 08/26/2000
• Status: Active Grant

• Current Assignee: RGB Systems Incorporated
• Original Assignee: RGB Systems Incorporated
• Inventors: Truong, Duy Duc, Taraci, Brian Richard
• Granted Patent: US 6,441,658 B1
• Time in Patent Office: Days
• US Class Current: 348/511
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H03L 7/235 Nested phase locked loops
• CPC Class Codes: H04N 21/4113 PC
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/126 whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/268 Signal distribution or switching
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 5/74 Projection arrangements for image reproduction, e.g. using eidophor
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 7/104 Switchers or splitters
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 Multi-standard receivers

Abstract

This invention describes a method and apparatus for vertically locking input and output video frame rates. The output vertical sync pulse is locked in phase with the input vertical sync pulse, regardless of the input format and frequency. The output resolution, horizontal refresh rate, and delay are all user selectable. Two Phase Locked Loops are connected in series to achieve vertical lock between the input and output frames. Locking the vertical sync pulses between the input and output frames will eliminate mixing of pixels from different input frames in one output frame. The first Phase Locked Loop generates the output pixel clock required to satisfy the user'"'"'s display preferences but may not precisely represent the desired output pixel clock required for frame locking because current Phase Locked Loops use integer dividers. A second Phase Locked Loop adjusts its output, which is the reference frequency to the first Phase Locked Loop, until a lock is achieved. A free running oscillator measures the frequency of the incoming video and sends its output to a micro-controller that computes the divider required in the first Phase Locked Loop based on user selected output resolution. The user may also adjust the delay between the vertical input and output video frames.

Claims

1. A method for vertically locking signals comprising:

obtaining input signal having input vertical sync pulse;

generating a pixel clock frequency from a reference frequency;

determining output vertical sync pulse from said pixel clock frequency;

generating said reference frequency to obtain a lock between said input vertical sync pulse and said output vertical sync pulse.

2. The method of claim 1 wherein said generating said reference frequency comprises:

generating a nominal frequency from a frequency generator;

comparing said input vertical sync pulse and said output vertical sync pulse to generate a phase error signal;

generating an adjustment signal by conditioning said phase error signal; and

adjusting said frequency generator to generate said reference frequency using said adjustment signal.

3. The method of claim 1 Wherein said reference frequency is further divided by a reference divider.

4. The method of claim 3 Wherein said reference divider is any positive integer number.

5. The method of claim 4 wherein said generating a pixel clock frequency comprises:

comparing said reference frequency with an adjusted pixel clock frequency to generate a phase error signal, wherein said adjusted pixel clock frequency is generated by dividing said pixel clock frequency by a PLL Divider;

generating an adjustment signal by conditioning said phase error signal; and

adjusting said pixel clock frequency using said adjustment signal.

6. The method of claim 5 wherein said PLL Divider is derived by:

determining the input vertical frequency;

obtaining the desired output horizontal resolution and the desired output vertical resolution;

generating an intermediate divider value by dividing the product of said input vertical frequency, said desired output horizontal resolution, said desired output vertical resolution, and said reference divider, by said nominal frequency; and

setting the PLL divider to the integer portion of said intermediate divider value.

7. The method of claim 6 wherein said determining the input vertical frequency comprises counting the number of pulses of a free running oscillator between two adjacent input vertical sync pulses.

8. The method of claim 6 wherein the user provides said desired output horizontal resolution and said desired output vertical resolution, said output horizontal resolution and said output vertical resolution having the pixels required for blanking.

9. The method of claim 1 wherein said determining output vertical sync pulse comprises:

obtaining the desired output horizontal resolution and the desired output vertical resolution;

generating a pixel counter by counting the cycles of said pixel clock;

generating output horizontal sync pulse from said pixel counter;

generating a line counter by counting said output horizontal sync pulse;

generating said output vertical sync pulse from said line counter;

restarting said pixel counter when said pixel counter reaches the desired output horizontal resolution; and

restarting said line counter when said line counter reaches the desired output vertical resolution.

10. The method of claim 9 wherein the user provides said desired output horizontal resolution and said desired output vertical resolution, said output horizontal resolution and said output vertical resolution having the pixels required for blanking.

11. The method of claim 9 wherein said generating output horizontal sync pulse comprises:

asserting said horizontal sync pulse when said pixel counter is equivalent to a user programmable horizontal sync start number; and

resetting said horizontal sync pulse when said pixel counter is equivalent to a user programmable horizontal sync end number.

12. The method of claim 9 wherein said generating output vertical sync pulse comprises:

asserting said vertical sync pulse when said line counter is equivalent to a user programmable vertical sync start number; and

resetting said vertical sync pulse when said line counter is equivalent to a user programmable vertical sync end number, wherein said start number and said end number may be adjusted to cause a phase shift between said input vertical sync pulse and said output vertical pulse.

14. The system of claim 13 wherein said adjusting said reference frequency comprises:

generating a nominal frequency from a frequency generator;

comparing said input vertical sync pulses and said output vertical sync pulses to generate a phase error signal;

generating an adjustment signal by conditioning said phase error signal; and

adjusting said frequency generator to generate said reference frequency using said adjustment signal.

15. The system of claim 13 wherein said reference frequency is further divided by a reference divider value.

16. The system of claim 15 wherein said reference divider value is any positive integer number.

17. The system of claim 16, further comprising a micro-controller, wherein said micro-controller selects said reference divider value.

18. The system of claim 17 wherein said generating clock pulses comprises:

said clock generator comparing said reference frequency with an adjusted clock frequency to generate a phase error signal, wherein said adjusted clock frequency is generated by dividing said clock pulses by a PLL Divider;

.

said clock generator generating an adjustment signal by conditioning said phase error signal; and

said clock generator adjusting said clock pulses using said adjustment signal.

19. The system of claim 18 wherein said PLL Divider is derived by said micro-controller and comprises:

determining the input vertical frequency;

obtaining the desired output horizontal resolution and the desired output vertical resolution;

generating an intermediate divider value by dividing the product of said input vertical frequency, said desired output horizontal resolution, said desired output vertical resolution, and said reference divider, by said nominal frequency; and

setting the PLL divider to the integer portion of said intermediate divider value.

20. The system of claim 19 wherein said determining the input vertical frequency comprises counting the number of pulses of a free running oscillator between two adjacent input vertical sync pulses and multiplying by the frequency of said free running oscillator.

21. The system of claim 19 wherein the user provides said desired output horizontal resolution and said desired output vertical resolution, said output horizontal resolution and said output vertical resolution having the pixels required for blanking.

22. The system of claim 17 wherein said micro-controller performs said generating output vertical sync pulses comprising:

obtaining the desired output horizontal resolution and the desired output vertical resolution;

generating a pixel counter by counting the cycles of said clock pulses;

generating output horizontal sync pulse from said pixel counter;

generating a line counter by counting said output horizontal sync pulses;

generating said output vertical sync pulse from said line counter;

restarting said pixel counter when said pixel counter reaches the desired output horizontal resolution; and

restarting said line counter when said line counter reaches the desired output vertical resolution.

23. The system of claim 22 wherein the user provides said desired output horizontal resolution and said desired output vertical resolution, said output horizontal resolution and said output vertical resolution having the pixels required for blanking.

24. The system of claim 22 wherein said generating output horizontal sync pulse comprises:

asserting said horizontal sync pulse when said pixel counter is equivalent to a user programmable horizontal sync start number; and

resetting said horizontal sync pulse when said pixel counter is equivalent to a user programmable horizontal sync end number.

25. The system of claim 22 wherein said generating output vertical sync pulse comprises:

asserting said vertical sync pulse when said line counter is equivalent to a user programmable vertical sync start number; and

resetting said vertical sync pulse when said line counter is equivalent to a user programmable vertical sync end number, wherein said start number and said end number may be adjusted to cause a phase shift between said input vertical sync pulse and said output vertical pulse.

13. A system for vertically locking signals comprising:

an input signal comprising input vertical sync pulses;

a clock generator for generating clock pulses from a reference frequency;

an output timing generator for generating output vertical sync pulses from said clock pulses;

a detector coupled to said output timing generator and said input signal for comparing said output vertical sync pulses and said input vertical sync pulses; and

an adjuster coupled to said detector, said adjuster configured to adjust said clock pulses by adjusting said reference frequency so that said input vertical sync pulses and said output vertical sync pulses are synchronized.