Method and apparatus for reducing clock speed and power consumption

• US 20020041599A1
• Filed: 05/17/2001
• Published: 04/11/2002
• Est. Priority Date: 10/03/2000
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Altima Communications, Inc. (Broadcom, Inc.)
• Inventors: Chang, Michael, Sokol, Michael A.
• Granted Patent: US 7,274,705 B2
• Time in Patent Office: Days
• US Class Current: 370/413
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 2205/064 Linked list, i.e. structure using pointers, e.g. allowing non-contiguous address segments in one logical buffer or dynamic buffer space allocation
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 2012/5682 Threshold; Watermark
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the first clock speed. A transmit buffer is in communication with the core and configured to receive signals from the core at the first clock speed. A sync is configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync is in communication with the transmit buffer and the receive buffer.

Claims

1. A system comprising:

a core that transmits and receives signals at a first clock speed;

a receive buffer in communication with said core and configured to transmit said signals to said core at said first clock speed;

a transmit buffer in communication with said core and configured to receive signals from said core at said first clock speed; and

a sync configured to allow signals to be received in said receive buffer at a second clock speed and to allow signals to be transmitted from said transmit buffer at said second clock speed, said sync in communication with said transmit buffer and said receive buffer.

2. The system as recited in claim 1 wherein said transmit buffer comprises a transmit FIFO.

3. The system as recited in claim 1 wherein said receive buffer comprises a receive FIFO.

4. The system as recited in claim 1 wherein said signals comprise command signals.

5. The system as recited in claim 1 wherein said signals comprise data signals.

6. The system as recited in claim 1 wherein said sync is configured to latch said signals at said second clock speed and hold said signals long enough to allow said core to transmit signals to said transmit buffer at said first clock speed.

7. The system as recited in claim 1 further comprising:

a command bus in communication with said sync;

a data bus in communication with said sync;

a processor in communication with said command bus and said data bus, said processor including,

a bus arbitrator in communication with said command bus and said data bus to receive, transmit and manage signals transferred along said command bus and said data bus; and

an access controller in communication with said bus arbitrator to process said signals.

8. A method for syncing two clock speeds, said method comprising the steps of:

receiving a signal in a receive buffer at a first clock speed using a sync;

transmitting said signal from said receive buffer to a core at a second clock speed;

transmitting said signal from said core to a transmit buffer at said second clock speed; and

transmitting said signal from said transmit buffer at said first clock speed using said sync.

9. The method as recited in claim 8 wherein said step of receiving a signal in a receive buffer comprises the step of receiving a signal in a receive FIFO.

10. The method as recited in claim 8 wherein said step of transmitting said signal to a transmit buffer comprises the step of transmitting said signal to a transmit FIFO.

11. The method as recited in claim 8 wherein said step of receiving a signal comprises the step of receiving command signals.

12. The method as recited in claim 8 wherein said step of receiving a signal comprises the step of receiving data signals.

13. The method as recited in claim 8 further comprising the step of holding said signal using said sync which latches said signal at said first clock speed and holds said signal long enough to allow said core to transmit signals to said transmit buffer at said second clock speed.

15. The system as recited in claim 14 wherein said signal receiving means receives said signal in a receive FIFO.

16. The system as recited in claim 14 wherein said transmit buffer transmitting means transmits said signal to a transmit FIFO.

17. The system as recited in claim 14 wherein said signal receiving means receives command signals.

18. The system as recited in claim 14 wherein said signal receiving means receives data signals.

20. The system as recited in claim 14 further comprising a holding means for holding said signal using said sync which latches said signal at said first clock speed and holds said signal long enough to allow said core to transmit signals to said transmit buffer at said second clock speed.

14. A system for syncing two clock speeds, said system comprising:

a signal receiving means for receiving a signal in a receive buffer at a first clock speed using a sync;

a core transmitting means for transmitting said signal from said receive buffer to a core at a second clock speed;

a transmit buffer transmitting means for transmitting said signal from said core to a transmit buffer at said second clock speed; and

a processor transmitting means for transmitting said signal from said transmit buffer at said first clock speed using said sync.