Method of manufacturing a semiconductor device using anti-reflective layer and self-aligned contact technique and semiconductor device manufactured thereby
First Claim
1. A method of manufacturing a semiconductor device, comprising the steps of:
- forming, in sequential order, a gate insulating layer, a first conductive layer, an etch stop layer, a hard mask layer, and an anti-reflective layer on a semiconductor substrate;
partially etching, in sequential order, said anti-reflective layer, said hard mask layer, and said etch stop layer, to form a plurality of parallel etch stop layer patterns and concurrently form a hard mask pattern and an anti-reflective pattern which are sequentially stacked on each of said etch stop layer patterns;
etching said anti-reflective layer pattern;
etching said first conductive layer to form a gate electrode under said etch stop layer patterns, with openings separating adjacent gate electrodes;
forming a conformal spacer insulating layer on the whole surface of said semiconductor substrate on which said gate electrodes are formed;
forming an interlayer insulating layer on said spacer insulating layer so as to fill in the openings between said gate electrodes; and
etching said interlayer insulating layer, said spacer insulating layer and said hard mask layer pattern using said etch stop layer patterns as a mask, thereby forming self-aligned contact holes exposing said semiconductor substrate between said gate electrodes, and forming spacers on side walls of said gate electrodes and said etch stop layer patterns.
1 Assignment
0 Petitions
Accused Products
Abstract
A method of manufacturing a semiconductor device includes sequential steps of forming a gate insulating layer, a first conductive layer, an etch stop layer, a hard mask layer, and an anti-reflective layer on a semiconductor substrate. The anti-reflective layer, hard mask layer, and etch stop layer are then partially etched according to a pattern to create an anti-reflective layer pattern, hard mask layer pattern, and etch stop layer pattern. The anti-reflective layer can be formed of a porous plasma silicon oxinitride layer to keep irregular reflections to a minimum. The anti-reflective layer pattern is then etched, followed by an etching of the first conductive layer to form a gate electrode under the etch stop layer pattern. A conformal spacer insulating layer is formed on the whole surface of the semiconductor substrate, and an interlayer insulating layer is formed on the spacer insulating layer so as to fill openings between the gate electrodes. The interlayer insulating layer, the spacer insulating layer and the hard mask pattern are etched using the etch stop layer pattern as an etch mask, and thereby forming self-aligned contact holes exposing the semiconductor substrate between the gate electrodes.
-
Citations
21 Claims
-
1. A method of manufacturing a semiconductor device, comprising the steps of:
-
forming, in sequential order, a gate insulating layer, a first conductive layer, an etch stop layer, a hard mask layer, and an anti-reflective layer on a semiconductor substrate;
partially etching, in sequential order, said anti-reflective layer, said hard mask layer, and said etch stop layer, to form a plurality of parallel etch stop layer patterns and concurrently form a hard mask pattern and an anti-reflective pattern which are sequentially stacked on each of said etch stop layer patterns;
etching said anti-reflective layer pattern;
etching said first conductive layer to form a gate electrode under said etch stop layer patterns, with openings separating adjacent gate electrodes;
forming a conformal spacer insulating layer on the whole surface of said semiconductor substrate on which said gate electrodes are formed;
forming an interlayer insulating layer on said spacer insulating layer so as to fill in the openings between said gate electrodes; and
etching said interlayer insulating layer, said spacer insulating layer and said hard mask layer pattern using said etch stop layer patterns as a mask, thereby forming self-aligned contact holes exposing said semiconductor substrate between said gate electrodes, and forming spacers on side walls of said gate electrodes and said etch stop layer patterns. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21)
-
-
19. A semiconductor device, comprising:
-
a gate pattern formed on a semiconductor substrate, said gate pattern including a gate electrode, an etch stop layer pattern, and a hard mask pattern, which are sequentially disposed;
a spacer insulating layer disposed on said gate pattern;
spacers formed on side walls of said gate electrode and said etch stop layer pattern; and
conductive pads electrically connected with said semiconductor substrate to fill in openings in said gate electrode.
-
Specification