Method of manufacturing a semiconductor device using anti-reflective layer and self-aligned contact technique and semiconductor device manufactured thereby

• US 20020042196A1
• Filed: 04/16/2001
• Published: 04/11/2002
• Est. Priority Date: 12/07/2000
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Lee, Se-Hyeong
• Granted Patent: US 6,436,812 B1
• Time in Patent Office: Days
• US Class Current: 438/636
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A method of manufacturing a semiconductor device includes sequential steps of forming a gate insulating layer, a first conductive layer, an etch stop layer, a hard mask layer, and an anti-reflective layer on a semiconductor substrate. The anti-reflective layer, hard mask layer, and etch stop layer are then partially etched according to a pattern to create an anti-reflective layer pattern, hard mask layer pattern, and etch stop layer pattern. The anti-reflective layer can be formed of a porous plasma silicon oxinitride layer to keep irregular reflections to a minimum. The anti-reflective layer pattern is then etched, followed by an etching of the first conductive layer to form a gate electrode under the etch stop layer pattern. A conformal spacer insulating layer is formed on the whole surface of the semiconductor substrate, and an interlayer insulating layer is formed on the spacer insulating layer so as to fill openings between the gate electrodes. The interlayer insulating layer, the spacer insulating layer and the hard mask pattern are etched using the etch stop layer pattern as an etch mask, and thereby forming self-aligned contact holes exposing the semiconductor substrate between the gate electrodes.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

forming, in sequential order, a gate insulating layer, a first conductive layer, an etch stop layer, a hard mask layer, and an anti-reflective layer on a semiconductor substrate;

partially etching, in sequential order, said anti-reflective layer, said hard mask layer, and said etch stop layer, to form a plurality of parallel etch stop layer patterns and concurrently form a hard mask pattern and an anti-reflective pattern which are sequentially stacked on each of said etch stop layer patterns;

etching said anti-reflective layer pattern;

etching said first conductive layer to form a gate electrode under said etch stop layer patterns, with openings separating adjacent gate electrodes;

forming a conformal spacer insulating layer on the whole surface of said semiconductor substrate on which said gate electrodes are formed;

forming an interlayer insulating layer on said spacer insulating layer so as to fill in the openings between said gate electrodes; and

etching said interlayer insulating layer, said spacer insulating layer and said hard mask layer pattern using said etch stop layer patterns as a mask, thereby forming self-aligned contact holes exposing said semiconductor substrate between said gate electrodes, and forming spacers on side walls of said gate electrodes and said etch stop layer patterns.

2. The method of claim 1, wherein said first conductive layer is formed of one of a polysilicon layer and a polycide layer.

3. The method of claim 1, wherein said etch stop layer is formed of an insulating layer with an etch selectivity with respect to a silicon oxide layer.

4. The method of claim 1, wherein said etch stop layer is a silicon nitride layer formed by a low pressure CVD process.

5. The method of claim 1, wherein said hard mask layer is formed of a CVD oxide layer.

6. The method of claim 1, wherein said anti-reflective layer is formed of one of an inorganic anti-reflective layer and an organic anti-reflective layer.

7. The method of claim 6, wherein said inorganic anti-reflective layer is a silicon oxinitride layer formed by a plasma CVD process.

8. The method of claim 6, wherein said inorganic anti-reflective layer is formed to a thickness greater than 500Å

.

9. The method of claim 8, wherein said step of etching said anti-reflective layer pattern is performed using a dry etch process until said hard mask layer pattern is exposed.

10. The method of claim 8, wherein said step of etching said anti-reflective layer pattern is performed using a wet etch process until said hard mask layer pattern is exposed.

11. The method of claim 9, wherein said dry etch process is performed using one of CF₄ gas, and a mixed gas including SF₆ gas and CF₄ gas, as an etch gas.

12. The method of claim 10, wherein said wet etch process is performed using a solution of phosphoric acid (H₃PO₄).

13. The method of claim 11, wherein said step of etching said anti-reflective layer pattern and said step of etching said first conductive layer are performed by an in-situ process.

14. The method of claim 8, wherein said step of etching said anti-reflective layer pattern is performed for a time sufficient to reduce the thickness of a remaining anti-reflective layer pattern to less than 500Å

, and said remaining anti-reflective layer pattern is completely removed during said step of etching said first conductive layer.

15. The method of claim 6, wherein said inorganic anti-reflective layer is formed to a thickness less than 500Å

.

16. The method of claim 15, wherein said anti-reflective layer pattern is removed during said step of etching said first conductive layer.

17. The method of claim 13, wherein said in-situ process comprises:

loading said semiconductor substrate on which said anti-reflective pattern is formed, into an etch chamber;

injecting one of CF₄ gas, and a mixed gas including SF₆ gas and CF₄ gas, into said etch chamber to etch said anti-reflective layer pattern; and

etching said first conductive layer.

18. The method of claim 1, further comprising the steps of:

forming a second conductive layer on the whole surface of said semiconductor substrate so as to fill in said self-aligned contact holes after said self-aligned contact holes are formed; and

etching said second conductive layer and said interlayer insulating layer until said spacer insulating layer is exposed, to thereby form conductive pads in said self-aligned contact holes.

20. The semiconductor device of claim 19, further including a gate insulating layer disposed between said gate electrode and said semiconductor substrate.

21. The semiconductor device of claim 19, wherein said spacer insulating layer is a silicon nitride layer formed by a low pressure CVD process.

19. A semiconductor device, comprising:

a gate pattern formed on a semiconductor substrate, said gate pattern including a gate electrode, an etch stop layer pattern, and a hard mask pattern, which are sequentially disposed;

a spacer insulating layer disposed on said gate pattern;

spacers formed on side walls of said gate electrode and said etch stop layer pattern; and

conductive pads electrically connected with said semiconductor substrate to fill in openings in said gate electrode.