SYSTEM AND METHOD FOR PERFORMING TABLE LOOK-UPS USING A MULTIPLE DATA FETCH ARCHITECTURE

• US 20020042869A1
• Filed: 09/08/1997
• Published: 04/11/2002
• Est. Priority Date: 09/08/1997
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: TATE, LARRY R., THIERBACH, MARK ERNEST
• Granted Patent: US 6,467,035 B2
• Time in Patent Office: Days
• US Class Current: 711/220
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/355 Indexed addressing

Abstract

A novel table look-up/indirect addressing system and method uses a dual fetch Harvard architecture to accomplish one full table look-up access per instruction cycle. The offset access fetch, the indirect data fetch and the table offset and base address addition are all performed during a single cycle. The system and method also accommodate data accesses using packed (half word) offsets.

Claims

1. A method for use with a data processing system for accessing data from a data memory using indirect addressing wherein one full data access is made for every instruction cycle executed by said data processing system, said method including the steps of:

performing a dual data fetch during said instruction cycle, said dual data fetch including using a data pointer to a location in a first data memory to fetch a data word from said first data memory, said dual data fetch including fetching an offset value from a second data memory; and

updating said data pointer by adding a pointer associated with a base address to an offset value retrieved during a previous instruction cycle.

2. The method of claim 1 wherein said method defines a data pipeline, said method further including the step of priming said data pipeline.

3. The method of claim 1 further including the step of performing said offset value fetches every other instruction cycle to process packed offset values.

4. The method of claim 1 further including the step of storing said offset value in an intermediate data storage register.

5. A data processing system for accessing data from a first data memory, said system using indirect addressing wherein one full data access is made for every instruction cycle executed by said data processing system, said system comprising:

a pointer addressing unit for fetching an offset value from a second data memory;

a data addressing unit, incorporating a data pointer means for pointing to a location in said first data memory, said data addressing unit for fetching a data word from said first data memory, said data addressing unit including means for updating said data pointer by adding a pointer associated with a base address to an offset value retrieved during a previous instruction cycle; and

a dual fetch control for causing said data fetches by said pointer addressing unit and said data addressing unit to occur during a single instruction cycle.

6. A data processing system according to claim 5 further including a first data bus and a second data bus for transferring data to said pointer addressing unit and said data addressing unit, respectively, during a single instruction cycle.

7. A data processing system according to claim 5 further including a data arithmetic unit for processing said fetched data word.

8. A data processing system according to claim 5 further including means for performing said offset value fetches every other instruction cycle to process packed offset values.