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Silicon-on-insulator chip having an isolation barrier for reliability

  • US 20020043686A1
  • Filed: 06/11/2001
  • Published: 04/18/2002
  • Est. Priority Date: 01/20/1998
  • Status: Active Grant
First Claim
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1. A silicon-on-insulator (SOI) semiconductor chip comprising:

  • a peripheral edge;

    a substrate;

    an oxide layer on the substrate;

    a silicon layer on the oxide layer;

    an active area;

    an isolation barrier including a groove;

    (a) being disposed slightly inward of the peripheral edge of the chip, (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and (c) surrounding completely the active area of the chip, and a passivation layer on the silicon layer and extending to the groove.

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