Silicon-on-insulator chip having an isolation barrier for reliability
First Claim
1. A silicon-on-insulator (SOI) semiconductor chip comprising:
- a peripheral edge;
a substrate;
an oxide layer on the substrate;
a silicon layer on the oxide layer;
an active area;
an isolation barrier including a groove;
(a) being disposed slightly inward of the peripheral edge of the chip, (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and (c) surrounding completely the active area of the chip, and a passivation layer on the silicon layer and extending to the groove.
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Abstract
An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.
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Citations
38 Claims
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1. A silicon-on-insulator (SOI) semiconductor chip comprising:
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a peripheral edge;
a substrate;
an oxide layer on the substrate;
a silicon layer on the oxide layer;
an active area;
an isolation barrier including a groove;
(a) being disposed slightly inward of the peripheral edge of the chip, (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and (c) surrounding completely the active area of the chip, and a passivation layer on the silicon layer and extending to the groove. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A silicon-on-insulator (SOI) semiconductor chip comprising:
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a peripheral edge;
a substrate;
an oxide layer on the substrate;
a silicon layer on the oxide layer;
a passivation layer on the silicon layer;
an active area including a gate located above the silicon layer, a gate metal contact located above and forming an electrical contact with the gate, and at least one metal contact located above and forming an electrical contact with the silicon layer;
an isolation barrier, including a groove;
(a) being disposed slightly inward of the peripheral edge of the chip, (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and (c) surrounding completely the active area of the chip;
a barrier material located (I) over the passivation layer on the silicon layer, and (ii) in the groove, presenting an additional barrier to impurities in the oxide layer outside the groove from diffusing into the oxide layer inside the groove.
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22. A silicon-on-insulator (SOI) semiconductor chip comprising:
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a peripheral edge;
a substrate;
an oxide layer on the substrate;
a silicon layer on the oxide layer;
a passivation layer on the silicon layer;
an active area;
an isolation barrier, including a groove;
(a) being disposed slightly inward of the peripheral edge of the chip, (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and (c) surrounding completely the active area of the chip;
a barrier material located;
(a) over the passivation layer on the silicon layer, and (b) in the groove, presenting an additional barrier to impurities in the oxide layer outside the groove from diffusing into the oxide layer inside the groove. - View Dependent Claims (23, 24, 25, 26, 27, 29, 30, 31, 32, 33, 34, 35)
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28. A silicon-on-insulator (SOI) semiconductor chip comprising:
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a peripheral edge;
a substrate;
an oxide layer on the substrate;
a silicon layer on the oxide layer;
an active area;
an isolation barrier;
(a) including a groove defined by side walls and an open bottom, (b) being disposed slightly inward of the peripheral edge of the chip, (c) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and (d) surrounding completely the active area of the chip;
a passivation layer on the silicon layer and the side walls of the groove with the bottom of the groove devoid of the passivation layer;
a doped conductive fill material located in the groove adjacent the passivation layer on the sidewalls of the groove forming an electrical contact with the substrate and contacting the substrate through the open bottom of the groove; and
a metal contact extending from the doped conductive fill material and forming an electrical contact with the doped conductive fill material.
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36. A silicon-on-insulator (SOI) semiconductor chip comprising:
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a peripheral edge;
a substrate;
an oxide layer on the substrate;
a silicon layer on the oxide layer;
an active area;
an isolation barrier, including a groove;
(a) being disposed slightly inward of the peripheral edge of the chip, (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and (c) surrounding completely the active area of the chip;
a passivation layer on the silicon layer and in the groove; and
a barrier material located in the passivation layer, over the silicon layer, and in the groove presenting an additional barrier to impurities in the oxide layer outside the groove from diffusing into the oxide layer inside the groove.
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37. A silicon-on-insulator (SOI) semiconductor chip comprising:
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a peripheral edge;
a substrate;
an oxide layer on the substrate;
a silicon layer on the oxide layer;
an active area;
an isolation barrier, including a groove;
(a) being disposed slightly inward of the pheriphal edge of the chip, (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and (c) surrounding completely the active area of the chip.
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38. A silicon-on-insulator (SOI) semiconductor chip comprising:
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a peripheral edge;
a substrate;
an oxide layer on the substrate;
a silicon layer on the oxide layer;
an active area;
an isolation barrier, including a groove;
(a) being disposed slightly inward of the pheriphal edge of the chip, (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and (c) surrounding completely the active area of the chip; and
a passivation layer on the silicon layer and extending to and partially over the groove.
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Specification