Semiconductor device and method for manufacturing the same

• US 20020043700A1
• Filed: 12/05/2001
• Published: 04/18/2002
• Est. Priority Date: 08/29/1997
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Minami, Toshifumi, Sasaki, Miki
• Granted Patent: US 6,879,025 B2
• Time in Patent Office: Days
• US Class Current: 257/620
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.

Claims

1. A semiconductor device comprising:

a dicing region provided on a semiconductor substrate;

a plurality of first dummy patterns formed on a surface of the semiconductor substrate within the dicing region; and

a plurality of second dummy patterns formed above the semiconductor substrate within the dicing region so as to correspond to the plurality of first dummy patters, respectively.

2. The semiconductor device according to claim 1, wherein the plurality of first dummy patterns and the plurality of second dummy patterns are each projected.

3. The semiconductor device according to claim 1, wherein the dicing region separates a plurality of semiconductor chips from each other, the semiconductor chips each having a gate portion and being formed on the semiconductor substrate.

4. The semiconductor device according to claim 3, wherein the plurality of first dummy patterns each have a structure which is substantially similar to that of the gate portion.

5. The semiconductor device according to claim 4, wherein the plurality of first dummy patterns each have a laminated structure including a gate oxide film, a polysilicon film, a Wsi film, and a SiN film.

6. The semiconductor device according to claim 1, wherein an element isolation region having an STI structure is formed by each side of the plurality of first dummy patterns.

7. The semiconductor device according to claim 5, wherein the plurality of first dummy patterns and the element isolation regions are arranged alternately to form a repetitive pattern.

8. The semiconductor device according to claim 1, wherein the plurality of second dummy patterns are protection films provided on the semiconductor substrate.

9. The semiconductor device according to claim 1, wherein the plurality of second dummy patterns include insulation films deposited on the semiconductor substrate.

10. The semiconductor device according to claim 1,wherein the plurality of first dummy patterns and the plurality of second dummy patterns are arranged at regular intervals.

11. The semiconductor device according to claim 10, wherein the plurality of first dummy patterns and the plurality of second dummy patterns are arranged at intervals of 1.5 μ

m or less.

12. The semiconductor device according to claim 1, wherein the plurality of first dummy patterns and the plurality of second dummy patterns are formed along a dicing direction of the dicing region.

13. The semiconductor device according to claim 1, wherein the plurality of first dummy patterns and the plurality of second dummy patterns prevent a large waste from being caused due to a crack during a dicing operation.